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Message-Id: <20230419111111.477118-15-dfustini@baylibre.com>
Date: Wed, 19 Apr 2023 04:11:04 -0700
From: Drew Fustini <dfustini@...libre.com>
To: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Ved Shanbhogue <ved@...osinc.com>,
Kornel Dulęba <mindal@...ihalf.com>,
Adrien Ricciardi <aricciardi@...libre.com>,
Nicolas Pitre <npitre@...libre.com>,
Fenghua Yu <fenghua.yu@...el.com>,
Reinette Chatre <reinette.chatre@...el.com>,
Babu Moger <babu.moger@....com>,
Peter Newman <peternewman@...gle.com>, x86@...nel.org,
Rob Herring <robh+dt@...nel.org>,
James Morse <james.morse@....com>
Cc: Drew Fustini <dfustini@...libre.com>
Subject: [RFC PATCH 14/21] DO_NOT_MERGE dt-bindings: soc: add Foobar SoC cache controller
Add bindings for an example SoC cache controller that implements CBQRI.
Co-developed-by: Adrien Ricciardi <aricciardi@...libre.com>
Signed-off-by: Adrien Ricciardi <aricciardi@...libre.com>
Signed-off-by: Drew Fustini <dfustini@...libre.com>
---
.../soc/foobar/foobar,cache-controller.yaml | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/foobar/foobar,cache-controller.yaml
diff --git a/Documentation/devicetree/bindings/soc/foobar/foobar,cache-controller.yaml b/Documentation/devicetree/bindings/soc/foobar/foobar,cache-controller.yaml
new file mode 100644
index 000000000000..6348483bbe09
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/foobar/foobar,cache-controller.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/foobar/foobar,cache-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Foobar SoC Cache Controller
+
+maintainers:
+ - Drew Fustini <dfustini@...libre.com>
+
+description:
+ Foobar SoC cache controller implements the RISC-V CBQRI interface for
+ capacity allocaiton and usage monitoring.
+
+allOf:
+ - $ref: /schemas/cache-controller.yaml#
+ - $ref: /schemas/riscv/riscv,cbqri.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: foobar,cache-controller
+ reg:
+ maxItems: 1
+ description: A memory region containing registers as defined in CBQRI spec
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+
+ cache-controller@...12000 {
+ compatible = "foobar,cache-controller";
+ reg = <0xfff12000 0x2000>;
+ cache-level = <2>;
+ riscv,cbqri-rcid = <64>;
+ riscv,cbqri-mcid = <256>;
+ };
+
+...
--
2.34.1
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