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Message-Id: <20230419111111.477118-21-dfustini@baylibre.com>
Date: Wed, 19 Apr 2023 04:11:10 -0700
From: Drew Fustini <dfustini@...libre.com>
To: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Ved Shanbhogue <ved@...osinc.com>,
Kornel Dulęba <mindal@...ihalf.com>,
Adrien Ricciardi <aricciardi@...libre.com>,
Nicolas Pitre <npitre@...libre.com>,
Fenghua Yu <fenghua.yu@...el.com>,
Reinette Chatre <reinette.chatre@...el.com>,
Babu Moger <babu.moger@....com>,
Peter Newman <peternewman@...gle.com>, x86@...nel.org,
Rob Herring <robh+dt@...nel.org>,
James Morse <james.morse@....com>
Cc: Drew Fustini <dfustini@...libre.com>
Subject: [RFC PATCH 20/21] DO_NOT_MERGE riscv: dts: qemu: add cbqri-capable controllers
Add nodes to for CBQRI-capable cache and memory controllers.
This is necessary as the qemu branch riscv-cbqri-rfc (based on
v8.0.0-rc4) does not yet support generating a dtb with the nodes and
properties needed for CBQRI controllers.
Thus, an external dtb (qemu-virt-cbqri.dtb) built by Linux is used when
invoking qemu-system-riscv64:
qemu-system-riscv64 \
-M virt \
-nographic \
-smp 8 \
-bios output/images/fw_jump.elf \
-kernel ${LINUX}/arch/riscv/boot/Image \
-dtb ${LINUX}/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dtb \
-append "root=/dev/vda ro" \
-drive file=output/images/rootfs.ext2,format=raw,id=hd0 \
-device virtio-blk-device,drive=hd0 \
Link: https://gitlab.baylibre.com/baylibre/qemu/-/tree/riscv-cbqri-rfc
Co-developed-by: Adrien Ricciardi <aricciardi@...libre.com>
Signed-off-by: Adrien Ricciardi <aricciardi@...libre.com>
Signed-off-by: Drew Fustini <dfustini@...libre.com>
---
arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts | 59 ++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts b/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts
index 400ed48a06af..2c4ddc4271cc 100644
--- a/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts
+++ b/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts
@@ -367,5 +367,64 @@ clint@...0000 {
reg = <0x00 0x2000000 0x00 0x10000>;
compatible = "sifive,clint0\0riscv,clint0";
};
+
+ cluster0_l2: controller@...0000 {
+ compatible = "foobar,cache-controller";
+ reg = <0x0 0x4820000 0x0 0x1000>; /* 4KB at 0x04820000 */
+ cache-unified;
+ cache-line-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1000>;
+ cache-size = <768000>; /* 750 KiB */
+ next-level-cache = <&shared_llc>;
+ riscv,cbqri-rcid = <64>;
+ riscv,cbqri-mcid = <256>;
+ };
+
+ cluster1_l2: controller@...1000 {
+ compatible = "foobar,cache-controller";
+ reg = <0x0 0x4821000 0x0 0x1000>; /* 4KB at 0x04821000 */
+ cache-unified;
+ cache-line-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1000>;
+ cache-size = <768000>; /* 750 KiB */
+ next-level-cache = <&shared_llc>;
+ riscv,cbqri-rcid = <64>;
+ riscv,cbqri-mcid = <256>;
+ };
+
+ shared_llc: controller@...b000 {
+ compatible = "foobar,cache-controller";
+ reg = <0x0 0x482b000 0x0 0x1000>; /* 4KB at 0x0482B000 */
+ cache-unified;
+ cache-line-size = <64>;
+ cache-level = <3>;
+ cache-sets = <4096>;
+ cache-size = <3145728>; /* 3 MiB */
+ riscv,cbqri-rcid = <64>;
+ riscv,cbqri-mcid = <256>;
+ };
+
+ mem0: controller@...8000 {
+ compatible = "foobar,memory-controller";
+ reg = <0x0 0x4828000 0x0 0x1000>; /* 4KB at 0x04828000 */
+ riscv,cbqri-rcid = <64>;
+ riscv,cbqri-mcid = <256>;
+ };
+
+ mem1: controller@...9000 {
+ compatible = "foobar,memory-controller";
+ reg = <0x0 0x4829000 0x0 0x1000>; /* 4KB at 0x04829000 */
+ riscv,cbqri-rcid = <64>;
+ riscv,cbqri-mcid = <256>;
+ };
+
+ mem2: controller@...a000 {
+ compatible = "foobar,memory-controller";
+ reg = <0x0 0x482a000 0x0 0x1000>; /* 4KB at 0x0482A000 */
+ riscv,cbqri-rcid = <64>;
+ riscv,cbqri-mcid = <256>;
+ };
};
};
--
2.34.1
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