linux-kernel - Re: [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC

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Message-ID: <6ce407ab-0d2a-323f-61df-44b2ed8eb0ca@starfivetech.com>
Date:   Thu, 20 Apr 2023 15:10:45 +0800
From:   Mason Huo <mason.huo@...rfivetech.com>
To:     Conor Dooley <conor@...nel.org>
CC:     "Rafael J. Wysocki" <rafael@...nel.org>,
        Viresh Kumar <viresh.kumar@...aro.org>,
        Emil Renner Berthing <kernel@...il.dk>,
        "Rob Herring" <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Shengyu Qu <wiagn233@...look.com>, <linux-pm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-riscv@...ts.infradead.org>
Subject: Re: [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110
 SoC



On 2023/4/19 1:28, Conor Dooley wrote:
> Hey Mason,
> 
> Just one minor comment in passing..
> 
> On Mon, Apr 17, 2023 at 02:39:42PM +0800, Mason Huo wrote:
>> Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
>> It supports up to 4 cpu frequency loads.
>> 
>> Signed-off-by: Mason Huo <mason.huo@...rfivetech.com>
>> ---
>>  .../jh7110-starfive-visionfive-2.dtsi         | 17 ++++++++++
>>  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 33 +++++++++++++++++++
>>  2 files changed, 50 insertions(+)
>> 
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index cca1c8040801..b25e6d68ce53 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -227,3 +227,20 @@ &uart0 {
>>  	pinctrl-0 = <&uart0_pins>;
>>  	status = "okay";
>>  };
>> +
>> +&U74_1 {
>> +	cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&U74_2 {
>> +	cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&U74_3 {
>> +	cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&U74_4 {
>> +	cpu-supply = <&vdd_cpu>;
>> +};
>> +
> 
> Applying: riscv: dts: starfive: Add cpu scaling for JH7110 SoC
> /stuff/linux/.git/rebase-apply/patch:30: new blank line at EOF.
> +
> warning: 1 line adds whitespace errors.
> 
> Cheers,
> Conor.
> 
Hi Conor,

Will fix it soon.

Thanks
Mason