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Date: Fri, 21 Apr 2023 14:30:55 -0700
From: Kuogee Hsieh <quic_khsieh@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
<dri-devel@...ts.freedesktop.org>, <robdclark@...il.com>,
<sean@...rly.run>, <swboyd@...omium.org>, <dianders@...omium.org>,
<vkoul@...nel.org>, <daniel@...ll.ch>, <airlied@...il.com>,
<agross@...nel.org>, <andersson@...nel.org>
CC: <quic_abhinavk@...cinc.com>, <quic_sbillaka@...cinc.com>,
<marijn.suijten@...ainline.org>, <freedreno@...ts.freedesktop.org>,
<linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v1 4/5] drm/msm/dpu: calculate DSC encoder parameters
dynamically
On 4/21/2023 2:13 PM, Dmitry Baryshkov wrote:
> On 22/04/2023 00:07, Kuogee Hsieh wrote:
>>
>> On 4/20/2023 5:27 PM, Dmitry Baryshkov wrote:
>>> On 21/04/2023 02:25, Kuogee Hsieh wrote:
>>>> During DSC preparation, add run time calculation to figure out what
>>>> usage modes, split mode and merge mode, is going to be setup.
>>>>
>>>> Signed-off-by: Kuogee Hsieh <quic_khsieh@...cinc.com>
>>>> ---
>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 56
>>>> ++++++++++++++++-------------
>>>> 1 file changed, 32 insertions(+), 24 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>>>> index 2fdacf1..5677728 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>>>> @@ -529,17 +529,9 @@ void dpu_encoder_helper_split_config(
>>>> bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
>>>> {
>>>> struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
>>>> - int i, intf_count = 0, num_dsc = 0;
>>>> + struct msm_display_topology *topology = &dpu_enc->topology;
>>>> - for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
>>>> - if (dpu_enc->phys_encs[i])
>>>> - intf_count++;
>>>> -
>>>> - /* See dpu_encoder_get_topology, we only support 2:2:1
>>>> topology */
>>>> - if (dpu_enc->dsc)
>>>> - num_dsc = 2;
>>>> -
>>>> - return (num_dsc > 0) && (num_dsc > intf_count);
>>>> + return (topology->num_dsc > topology->num_intf);
>>>> }
>>>> static void dpu_encoder_get_topology(
>>>> @@ -1861,41 +1853,57 @@ static void dpu_encoder_prep_dsc(struct
>>>> dpu_encoder_virt *dpu_enc,
>>>> struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
>>>> struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
>>>> struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
>>>> + struct msm_display_topology *topology = &dpu_enc->topology;
>>>> int this_frame_slices;
>>>> int intf_ip_w, enc_ip_w;
>>>> - int dsc_common_mode;
>>>> + int dsc_common_mode = 0;
>>>> int pic_width;
>>>> u32 initial_lines;
>>>> + int num_dsc, num_intf;
>>>> int i;
>>>> for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
>>>> hw_pp[i] = dpu_enc->hw_pp[i];
>>>> hw_dsc[i] = dpu_enc->hw_dsc[i];
>>>> -
>>>> - if (!hw_pp[i] || !hw_dsc[i]) {
>>>> - DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
>>>> - return;
>>>> - }
>>>
>> Why?
>>
>> MAX_CHANNELS_PER_ENC == 2
>>
>> This works for dsi since it use 2 dsc encoder.
>>
>> Since DP only use one dsc encoder, this will cause it return at loop
>> 2 without execute dpu_encoder_dsc_pipe_cfg().
>
> Then the loop should go up to num_dsc rather than MAX_CHANNELS_PER_ENC
>
>>
>>>
>>>> }
>>>> - dsc_common_mode = 0;
>>>> + num_dsc = topology->num_dsc;
>>>> + num_intf = topology->num_intf;
>>>> +
>>>> pic_width = dsc->pic_width;
>>>> - dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
>>>> if (enc_master->intf_mode == INTF_MODE_VIDEO)
>>>> dsc_common_mode |= DSC_MODE_VIDEO;
>>>> + /*
>>>> + * If this encoder is driving more than one DSC encoder, they
>>>> + * operate in tandem, same pic dimension needs to be used by
>>>> + * each of them.(pp-split is assumed to be not supported)
>>>> + *
>>>> + */
>>>> +
>>>> this_frame_slices = pic_width / dsc->slice_width;
>>>> intf_ip_w = this_frame_slices * dsc->slice_width;
>>>> + enc_ip_w = intf_ip_w;
>>>> +
>>>> + intf_ip_w /= num_intf;
>>>> +
>>>> + if (num_dsc > 1)
>>>> + dsc_common_mode |= DSC_MODE_SPLIT_PANEL;
>>>> +
>>>> + if (dpu_encoder_use_dsc_merge(&dpu_enc->base)) {
>>>> + dsc_common_mode |= DSC_MODE_MULTIPLEX;
>>>> + /*
>>>> + * in dsc merge case: when using 2 encoders for the same
>>>> + * stream, no. of slices need to be same on both the
>>>> + * encoders.
>>>> + */
>>>> + enc_ip_w = intf_ip_w / 2;
>>>
>>> So do you want to get enc_ip_w / 2 or enc_ip_w / num_intf / 2 here?
>> enc_ip_w / num_intf / 2
>
> But previously we had enc_ip_w = intf_ip_w / 2. Was it because of the
> assumption that num_intf = 1?
i think so since there is no num_intf involve at previous code.
>
>>>
>>>> + }
>>>> - /*
>>>> - * dsc merge case: when using 2 encoders for the same stream,
>>>> - * no. of slices need to be same on both the encoders.
>>>> - */
>>>> - enc_ip_w = intf_ip_w / 2;
>>>> initial_lines = dpu_encoder_dsc_initial_line_calc(dsc,
>>>> enc_ip_w);
>>>> - for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
>>>> + for (i = 0; i < num_dsc; i++)
>>>> dpu_encoder_dsc_pipe_cfg(dpu_enc, hw_dsc[i], hw_pp[i], dsc,
>>>> dsc_common_mode, initial_lines);
>>>> }
>>>
>
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