linux-kernel - Re: [PATCH 3/6] drm: bridge: samsung-dsim: Fetch pll-clock-frequency automatically

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <28219b3d-e2cc-63b1-555b-c3845300f45a@samsung.com>
Date:   Fri, 21 Apr 2023 13:25:26 +0200
From:   Marek Szyprowski <m.szyprowski@...sung.com>
To:     Adam Ford <aford173@...il.com>, dri-devel@...ts.freedesktop.org
Cc:     marex@...x.de, aford@...conembedded.com,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        NXP Linux Team <linux-imx@....com>,
        Inki Dae <inki.dae@...sung.com>,
        Jagan Teki <jagan@...rulasolutions.com>,
        Andrzej Hajda <andrzej.hajda@...el.com>,
        Neil Armstrong <neil.armstrong@...aro.org>,
        Robert Foss <rfoss@...nel.org>,
        Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
        Jonas Karlman <jonas@...boo.se>,
        Jernej Skrabec <jernej.skrabec@...il.com>,
        David Airlie <airlied@...il.com>,
        Daniel Vetter <daniel@...ll.ch>, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/6] drm: bridge: samsung-dsim: Fetch
 pll-clock-frequency automatically

On 15.04.2023 12:41, Adam Ford wrote:
> Fetch the clock rate of "sclk_mipi" (or "pll_clk") instead of
> having an entry in the device tree for samsung,pll-clock-frequency.
>
> Signed-off-by: Adam Ford <aford173@...il.com>

This one breaks DSI panel operation on my Exynos-based Trats, Trats2 and 
TM2e boards. I've didn't check the details, but probably something is 
missing in the dts to make it working properly. Surprisingly the display 
is still working fine on Arndale board with DSI TC358764 bridge.

> ---
>   drivers/gpu/drm/bridge/samsung-dsim.c | 12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> index 9fec32b44e05..73f0c3fbbdf5 100644
> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> @@ -1744,11 +1744,6 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
>   	struct device_node *node = dev->of_node;
>   	int ret;
>   
> -	ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
> -				       &dsi->pll_clk_rate);
> -	if (ret < 0)
> -		return ret;
> -
>   	ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
>   				       &dsi->burst_clk_rate);
>   	if (ret < 0)
> @@ -1823,13 +1818,18 @@ int samsung_dsim_probe(struct platform_device *pdev)
>   		if (IS_ERR(dsi->clks[i])) {
>   			if (strcmp(clk_names[i], "sclk_mipi") == 0) {
>   				dsi->clks[i] = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME);
> -				if (!IS_ERR(dsi->clks[i]))
> +				if (!IS_ERR(dsi->clks[i])) {
> +					dsi->pll_clk_rate = clk_get_rate(dsi->clks[i]);
>   					continue;
> +				}
>   			}
>   
>   			dev_info(dev, "failed to get the clock: %s\n", clk_names[i]);
>   			return PTR_ERR(dsi->clks[i]);
>   		}
> +
> +		if (strcmp(clk_names[i], "sclk_mipi") == 0)
> +			dsi->pll_clk_rate = clk_get_rate(dsi->clks[i]);
>   	}
>   
>   	dsi->reg_base = devm_platform_ioremap_resource(pdev, 0);

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland