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Message-ID: <ZEKL1XzYzOwcEkHK@lpieralisi>
Date: Fri, 21 Apr 2023 15:12:53 +0200
From: Lorenzo Pieralisi <lpieralisi@...nel.org>
To: Sumit Gupta <sumitg@...dia.com>
Cc: treding@...dia.com, krzysztof.kozlowski@...aro.org,
dmitry.osipenko@...labora.com, viresh.kumar@...aro.org,
rafael@...nel.org, jonathanh@...dia.com, robh+dt@...nel.org,
helgaas@...nel.org, linux-kernel@...r.kernel.org,
linux-tegra@...r.kernel.org, linux-pm@...r.kernel.org,
devicetree@...r.kernel.org, linux-pci@...r.kernel.org,
mmaddireddy@...dia.com, kw@...ux.com, bhelgaas@...gle.com,
vidyas@...dia.com, sanjayc@...dia.com, ksitaraman@...dia.com,
ishah@...dia.com, bbasu@...dia.com
Subject: Re: [Patch v6 7/9] PCI: tegra194: Fix possible array out of bounds
access
On Tue, Apr 11, 2023 at 04:30:00PM +0530, Sumit Gupta wrote:
> Add check to fix the possible array out of bounds violation by
> making speed equal to GEN1_CORE_CLK_FREQ when its value is more
> than the size of "pcie_gen_freq" array. This array has size of
> four but possible speed (CLS) values are from "0 to 0xF". So,
> "speed - 1" values are "-1 to 0xE". This change was suggested by
> "Bjorn Helgaas" in the below link.
There is a Suggested-by tag and a Link: tag remove the last
sentence, that's duplicate information.
> Suggested-by: Bjorn Helgaas <helgaas@...nel.org>
> Signed-off-by: Sumit Gupta <sumitg@...dia.com>
> Link: https://lore.kernel.org/lkml/72b9168b-d4d6-4312-32ea-69358df2f2d0@nvidia.com/
> ---
> drivers/pci/controller/dwc/pcie-tegra194.c | 13 +++++++++++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
Acked-by: Lorenzo Pieralisi <lpieralisi@...nel.org>
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 09825b4a075e..e6eec85480ca 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -223,6 +223,7 @@
> #define EP_STATE_ENABLED 1
>
> static const unsigned int pcie_gen_freq[] = {
> + GEN1_CORE_CLK_FREQ, /* PCI_EXP_LNKSTA_CLS == 0; undefined */
> GEN1_CORE_CLK_FREQ,
> GEN2_CORE_CLK_FREQ,
> GEN3_CORE_CLK_FREQ,
> @@ -459,7 +460,11 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
>
> speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
> PCI_EXP_LNKSTA_CLS;
> - clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
> +
> + if (speed >= ARRAY_SIZE(pcie_gen_freq))
> + speed = 0;
> +
> + clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]);
>
> if (pcie->of_data->has_ltr_req_fix)
> return IRQ_HANDLED;
> @@ -1020,7 +1025,11 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
>
> speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
> PCI_EXP_LNKSTA_CLS;
> - clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
> +
> + if (speed >= ARRAY_SIZE(pcie_gen_freq))
> + speed = 0;
> +
> + clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]);
>
> tegra_pcie_enable_interrupts(pp);
>
> --
> 2.17.1
>
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