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Message-ID: <aa3c1fda-553b-fa71-21dc-41d1244007a4@suse.com>
Date: Mon, 24 Apr 2023 12:37:34 +0200
From: Matthias Brugger <mbrugger@...e.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Chester Lin <clin@...e.com>,
Andreas Färber <afaerber@...e.de>,
NXP S32 Linux Team <s32@....com>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: s32: add missing cache properties
On 22/04/2023 00:32, Krzysztof Kozlowski wrote:
> As all level 2 and level 3 caches are unified, add required
> cache-unified properties to fix warnings like:
>
> s32g274a-evb.dtb: l2-cache1: 'cache-unified' is a required property
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Reviewed-by: Matthias Brugger <mbrugger@...e.com>
>
> ---
>
> Please take the patch via sub-arch SoC tree.
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 ++
> arch/arm64/boot/dts/freescale/s32v234.dtsi | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index d8c82da88ca0..5ac1cc9ff50e 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -53,11 +53,13 @@ cpu3: cpu@101 {
> cluster0_l2: l2-cache0 {
> compatible = "cache";
> cache-level = <2>;
> + cache-unified;
> };
>
> cluster1_l2: l2-cache1 {
> compatible = "cache";
> cache-level = <2>;
> + cache-unified;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi
> index 3e306218d533..42409ec56792 100644
> --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi
> @@ -62,11 +62,13 @@ cpu3: cpu@101 {
> cluster0_l2_cache: l2-cache0 {
> compatible = "cache";
> cache-level = <2>;
> + cache-unified;
> };
>
> cluster1_l2_cache: l2-cache1 {
> compatible = "cache";
> cache-level = <2>;
> + cache-unified;
> };
> };
>
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