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Date: Tue, 25 Apr 2023 16:07:00 +0800
From: Jacky Huang <ychuang570808@...il.com>
To: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
Cc: Philipp Zabel <p.zabel@...gutronix.de>, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, lee@...nel.org,
mturquette@...libre.com, sboyd@...nel.org,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>, devicetree@...r.kernel.org,
linux-clk@...r.kernel.org, LKML <linux-kernel@...r.kernel.org>,
linux-serial <linux-serial@...r.kernel.org>, arnd@...db.de,
schung@...oton.com, mjchen@...oton.com,
Jacky Huang <ychuang3@...oton.com>
Subject: Re: [PATCH v7 10/12] reset: Add Nuvoton ma35d1 reset driver support
Dear Ilpo,
On 2023/4/25 下午 03:40, Ilpo Järvinen wrote:
> On Tue, 25 Apr 2023, Jacky Huang wrote:
>
>>
>> On 2023/4/25 上午 03:21, Philipp Zabel wrote:
>>> Hi Jacky,
>>>
>>> On Wed, Apr 12, 2023 at 05:38:22AM +0000, Jacky Huang wrote:
>>>> From: Jacky Huang <ychuang3@...oton.com>
>>>>
>>>> This driver supports individual IP reset for ma35d1. The reset
>>>> control registers is a subset of system control registers.
>>>>
>>>> Signed-off-by: Jacky Huang <ychuang3@...oton.com>
>>>> ---
>>>>
>>>> +static const struct {
>>>> + unsigned long id;
>>> Why store the id? ids should be contiguous and should start at 0,
>>> so the id could just be an index into the array.
>> Thank you, I didn't notice that the IDs were already consecutive.
>> The id field is indeed unnecessary, and I will remove it.
> I recommend you still keep the IDs in the array initializer though, like
> this:
>
> ...
> } ma35d1_reset_map[] = {
> [MA35D1_RESET_CHIP] = {0x20, 0},
> [MA35D1_RESET_CA35CR0] = {0x20, 1},
> ...
Okay, I will modify the code like this.
>>>> + u32 reg_ofs;
>>>> + u32 bit;
>>>> +} ma35d1_reset_map[] = {
>>>> + { MA35D1_RESET_CHIP, 0x20, 0 },
>>>> + { MA35D1_RESET_CA35CR0, 0x20, 1 },
>>>> + { MA35D1_RESET_CA35CR1, 0x20, 2 },
>>>> + { MA35D1_RESET_CM4, 0x20, 3 },
>>>> + { MA35D1_RESET_PDMA0, 0x20, 4 },
>>>> + { MA35D1_RESET_PDMA1, 0x20, 5 },
>>>> + { MA35D1_RESET_PDMA2, 0x20, 6 },
>>>> + { MA35D1_RESET_PDMA3, 0x20, 7 },
>>>> + { MA35D1_RESET_DISP, 0x20, 9 },
>>>> + { MA35D1_RESET_VCAP0, 0x20, 10 },
>>>> + { MA35D1_RESET_VCAP1, 0x20, 11 },
>>>> + { MA35D1_RESET_GFX, 0x20, 12 },
>>>> + { MA35D1_RESET_VDEC, 0x20, 13 },
>>>> + { MA35D1_RESET_WHC0, 0x20, 14 },
>>>> + { MA35D1_RESET_WHC1, 0x20, 15 },
>>>> + { MA35D1_RESET_GMAC0, 0x20, 16 },
>>>> + { MA35D1_RESET_GMAC1, 0x20, 17 },
>>>> + { MA35D1_RESET_HWSEM, 0x20, 18 },
>>>> + { MA35D1_RESET_EBI, 0x20, 19 },
>>>> + { MA35D1_RESET_HSUSBH0, 0x20, 20 },
>>>> + { MA35D1_RESET_HSUSBH1, 0x20, 21 },
>>>> + { MA35D1_RESET_HSUSBD, 0x20, 22 },
>>>> + { MA35D1_RESET_USBHL, 0x20, 23 },
>>>> + { MA35D1_RESET_SDH0, 0x20, 24 },
>>>> + { MA35D1_RESET_SDH1, 0x20, 25 },
>>>> + { MA35D1_RESET_NAND, 0x20, 26 },
>>>> + { MA35D1_RESET_GPIO, 0x20, 27 },
>>>> + { MA35D1_RESET_MCTLP, 0x20, 28 },
>>>> + { MA35D1_RESET_MCTLC, 0x20, 29 },
>>>> + { MA35D1_RESET_DDRPUB, 0x20, 30 },
>>>> + { MA35D1_RESET_TMR0, 0x24, 2 },
>>>> + { MA35D1_RESET_TMR1, 0x24, 3 },
>>>> + { MA35D1_RESET_TMR2, 0x24, 4 },
>>>> + { MA35D1_RESET_TMR3, 0x24, 5 },
>>>> + { MA35D1_RESET_I2C0, 0x24, 8 },
>>>> + { MA35D1_RESET_I2C1, 0x24, 9 },
>>>> + { MA35D1_RESET_I2C2, 0x24, 10 },
>>>> + { MA35D1_RESET_I2C3, 0x24, 11 },
>>>> + { MA35D1_RESET_QSPI0, 0x24, 12 },
>>>> + { MA35D1_RESET_SPI0, 0x24, 13 },
>>>> + { MA35D1_RESET_SPI1, 0x24, 14 },
>>>> + { MA35D1_RESET_SPI2, 0x24, 15 },
>>>> + { MA35D1_RESET_UART0, 0x24, 16 },
>>>> + { MA35D1_RESET_UART1, 0x24, 17 },
>>>> + { MA35D1_RESET_UART2, 0x24, 18 },
>>>> + { MA35D1_RESET_UAER3, 0x24, 19 },
>>>> + { MA35D1_RESET_UART4, 0x24, 20 },
>>>> + { MA35D1_RESET_UART5, 0x24, 21 },
>>>> + { MA35D1_RESET_UART6, 0x24, 22 },
>>>> + { MA35D1_RESET_UART7, 0x24, 23 },
>>>> + { MA35D1_RESET_CANFD0, 0x24, 24 },
>>>> + { MA35D1_RESET_CANFD1, 0x24, 25 },
>>>> + { MA35D1_RESET_EADC0, 0x24, 28 },
>>>> + { MA35D1_RESET_I2S0, 0x24, 29 },
>>>> + { MA35D1_RESET_SC0, 0x28, 0 },
>>>> + { MA35D1_RESET_SC1, 0x28, 1 },
>>>> + { MA35D1_RESET_QSPI1, 0x28, 4 },
>>>> + { MA35D1_RESET_SPI3, 0x28, 6 },
>>>> + { MA35D1_RESET_EPWM0, 0x28, 16 },
>>>> + { MA35D1_RESET_EPWM1, 0x28, 17 },
>>>> + { MA35D1_RESET_QEI0, 0x28, 22 },
>>>> + { MA35D1_RESET_QEI1, 0x28, 23 },
>>>> + { MA35D1_RESET_ECAP0, 0x28, 26 },
>>>> + { MA35D1_RESET_ECAP1, 0x28, 27 },
>>>> + { MA35D1_RESET_CANFD2, 0x28, 28 },
>>>> + { MA35D1_RESET_ADC0, 0x28, 31 },
>>>> + { MA35D1_RESET_TMR4, 0x2C, 0 },
>>>> + { MA35D1_RESET_TMR5, 0x2C, 1 },
>>>> + { MA35D1_RESET_TMR6, 0x2C, 2 },
>>>> + { MA35D1_RESET_TMR7, 0x2C, 3 },
>>>> + { MA35D1_RESET_TMR8, 0x2C, 4 },
>>>> + { MA35D1_RESET_TMR9, 0x2C, 5 },
>>>> + { MA35D1_RESET_TMR10, 0x2C, 6 },
>>>> + { MA35D1_RESET_TMR11, 0x2C, 7 },
>>>> + { MA35D1_RESET_UART8, 0x2C, 8 },
>>>> + { MA35D1_RESET_UART9, 0x2C, 9 },
>>>> + { MA35D1_RESET_UART10, 0x2C, 10 },
>>>> + { MA35D1_RESET_UART11, 0x2C, 11 },
>>>> + { MA35D1_RESET_UART12, 0x2C, 12 },
>>>> + { MA35D1_RESET_UART13, 0x2C, 13 },
>>>> + { MA35D1_RESET_UART14, 0x2C, 14 },
>>>> + { MA35D1_RESET_UART15, 0x2C, 15 },
>>>> + { MA35D1_RESET_UART16, 0x2C, 16 },
>>>> + { MA35D1_RESET_I2S1, 0x2C, 17 },
>>>> + { MA35D1_RESET_I2C4, 0x2C, 18 },
>>>> + { MA35D1_RESET_I2C5, 0x2C, 19 },
>>>> + { MA35D1_RESET_EPWM2, 0x2C, 20 },
>>>> + { MA35D1_RESET_ECAP2, 0x2C, 21 },
>>>> + { MA35D1_RESET_QEI2, 0x2C, 22 },
>>>> + { MA35D1_RESET_CANFD3, 0x2C, 23 },
>>>> + { MA35D1_RESET_KPI, 0x2C, 24 },
>>>> + { MA35D1_RESET_GIC, 0x2C, 28 },
>>>> + { MA35D1_RESET_SSMCC, 0x2C, 30 },
>>>> + { MA35D1_RESET_SSPCC, 0x2C, 31 }
>>>> +};
Best Regards,
Jacky Huang
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