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Message-ID: <CAGuA+oo0w8n9zEKdd1UfYx+F08wK4CcUGqRbBi4C-xNYp+vtDA@mail.gmail.com>
Date: Tue, 25 Apr 2023 13:28:39 +0200
From: Balsam CHIHI <bchihi@...libre.com>
To: Chen-Yu Tsai <wenst@...omium.org>
Cc: Nícolas F. R. A. Prado
<nfraprado@...labora.com>, daniel.lezcano@...aro.org,
angelogioacchino.delregno@...labora.com, rafael@...nel.org,
amitk@...nel.org, rui.zhang@...el.com, matthias.bgg@...il.com,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
rdunlap@...radead.org, ye.xingchen@....com.cn,
p.zabel@...gutronix.de, linux-pm@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, devicetree@...r.kernel.org,
khilman@...libre.com, james.lo@...iatek.com,
rex-bc.chen@...iatek.com
Subject: Re: [PATCH 0/4] Add LVTS support for mt8192
On Tue, Apr 25, 2023 at 12:00 PM Chen-Yu Tsai <wenst@...omium.org> wrote:
>
> On Tue, Apr 25, 2023 at 6:21 AM Nícolas F. R. A. Prado
> <nfraprado@...labora.com> wrote:
> >
> > On Tue, Mar 28, 2023 at 02:20:24AM +0200, Balsam CHIHI wrote:
> > > On Sat, Mar 25, 2023 at 5:33 AM Chen-Yu Tsai <wenst@...omium.org> wrote:
> > > >
> > > > On Wed, Mar 22, 2023 at 8:48 PM Balsam CHIHI <bchihi@...libre.com> wrote:
> > > > >
> > > > > Hi Chen-Yu,
> > > > >
> > > > > I suspect the bug comes from incorrect calibration data offsets for AP
> > > > > Domain because you confirm that MCU Domain probe runs without issues.
> > > > > Is it possible to test something for us to confirm this theory (i
> > > > > don't have an mt8192 board on hand now), when you have the time of
> > > > > course?
> > > > > We would like to test AP Domain's calibration data offsets with a
> > > > > working one, for example :
> > > > >
> > > > > static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
> > > > > {
> > > > > - .cal_offset = { 0x25, 0x28 },
> > > > > + .cal_offset = { 0x04, 0x04 },
> > > > > .lvts_sensor = {
> > > > > { .dt_id = MT8192_AP_VPU0 },
> > > > > { .dt_id = MT8192_AP_VPU1 }
> > > > > @@ -1336,7 +1336,7 @@ static const struct lvts_ctrl_data
> > [..]
> > > > >
> > > > > This example is tested and works for mt8195,
> > > > > (all sensors use the same calibration data offset for testing purposes).
> > > > >
> > > > > Thank you in advance for your help.
> > > >
> > > > The MCU ones are still tripping though. If I change all of them to 0x04,
> > > > then nothing trips. There's also a bug in the interrupt handling code
> > > > that needs to be dealt with.
> > > >
> > > > AFAICT the calibration data is stored differently. If you look at ChromeOS's
> > > > downstream v5.10 driver, you'll see mt6873_efuse_to_cal_data() for MT8192,
> > > > and mt8195_efuse_to_cal_data() for MT8195. The difference sums up to:
> > > > MT8195 has all data sequentially stored, while MT8192 has most data stored
> > > > in lower 24 bits of each 32-bit word, and the highest 8 bits are then used
> > > > to pack data for the remaining sensors.
> > > >
> > > > Regards
> > > > ChenYu
> > >
> > > Hi Chen-Yu Tsai,
> > >
> > > Thank you very much for helping me testing this suggestion.
> > >
> > > Indeed, calibration data is stored differently in the mt8192 compared to mt8195.
> > > So, the mt8192's support will be delayed for now, to allow further debugging.
> > >
> > > In the mean time, we will only continue to upstream the remaining
> > > mt8195's source code, so it will get full LVTS support.
> > > A new series will be submitted soon.
> >
> > Hi Balsam,
> >
> > like Chen-Yu mentioned, the calibration data is stored with 4 byte alignment for
> > MT8192, but the data that is split between non-contiguous bytes is for the
> > thermal controllers (called Resistor-Capacitor Calibration downstream) not the
> > sensors. The controller calibration isn't currently handled in this driver (and
> > downstream it also isn't used, since a current value is read from the controller
> > instead), so we can just ignore those.
> >
> > The patch below adjusts the addresseses for the sensors and gives me reasonable
> > reads, so the machine no longer reboots. Can you integrate it into your series?
>
> Not sure what I got wrong, but on my machine the VPU0 and VPU1 zone interrupts
> are still tripping excessively. The readings seem normal though. Specifically,
> it's bits 16 and 17 that are tripping.
>
Hi Chen-Yu,
Thank you for testing!
As the readings are normal that proves that calibration data offsets
are correct.
would you like that I send the v2 of series to add mt8192 support?
Then we could deal with the interrupts later in a separate fix,
because the interrupt code in common for both SoC (mt8192 and mt8195)?
Does Nícolas also have tripping interrupts?
On my side, I've got no interrupts tripping on mt8195.
Any other suggestions (a question for everyone)?
Best regards,
Balsam
> > Thanks,
> > Nícolas
> >
> > From 4506f03b806f3eeb89887bac2c1c86d61da97281 Mon Sep 17 00:00:00 2001
> > From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
> > <nfraprado@...labora.com>
> > Date: Mon, 24 Apr 2023 17:42:42 -0400
> > Subject: [PATCH] thermal/drivers/mediatek/lvts_thermal: Fix calibration
> > offsets for MT8192
> > MIME-Version: 1.0
> > Content-Type: text/plain; charset=UTF-8
> > Content-Transfer-Encoding: 8bit
> >
> > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@...labora.com>
> > ---
> > drivers/thermal/mediatek/lvts_thermal.c | 14 +++++++-------
> > 1 file changed, 7 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
> > index b6956c89d557..f8afbc2ac190 100644
> > --- a/drivers/thermal/mediatek/lvts_thermal.c
> > +++ b/drivers/thermal/mediatek/lvts_thermal.c
> > @@ -1261,7 +1261,7 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
> >
> > static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
> > {
> > - .cal_offset = { 0x04, 0x07 },
> > + .cal_offset = { 0x04, 0x08 },
> > .lvts_sensor = {
> > { .dt_id = MT8192_MCU_BIG_CPU0 },
> > { .dt_id = MT8192_MCU_BIG_CPU1 }
> > @@ -1271,7 +1271,7 @@ static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
> > .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
> > },
> > {
> > - .cal_offset = { 0x0d, 0x10 },
> > + .cal_offset = { 0x0c, 0x10 },
> > .lvts_sensor = {
> > { .dt_id = MT8192_MCU_BIG_CPU2 },
> > { .dt_id = MT8192_MCU_BIG_CPU3 }
> > @@ -1281,7 +1281,7 @@ static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
> > .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
> > },
> > {
> > - .cal_offset = { 0x16, 0x19, 0x1c, 0x1f },
> > + .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
> > .lvts_sensor = {
> > { .dt_id = MT8192_MCU_LITTLE_CPU0 },
> > { .dt_id = MT8192_MCU_LITTLE_CPU1 },
> > @@ -1296,7 +1296,7 @@ static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
> >
> > static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
> > {
> > - .cal_offset = { 0x25, 0x28 },
> > + .cal_offset = { 0x24, 0x28 },
> > .lvts_sensor = {
> > { .dt_id = MT8192_AP_VPU0 },
> > { .dt_id = MT8192_AP_VPU1 }
> > @@ -1306,7 +1306,7 @@ static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
> > .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
> > },
> > {
> > - .cal_offset = { 0x2e, 0x31 },
> > + .cal_offset = { 0x2c, 0x30 },
> > .lvts_sensor = {
> > { .dt_id = MT8192_AP_GPU0 },
> > { .dt_id = MT8192_AP_GPU1 }
> > @@ -1316,7 +1316,7 @@ static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
> > .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
> > },
> > {
> > - .cal_offset = { 0x37, 0x3a },
> > + .cal_offset = { 0x34, 0x38 },
> > .lvts_sensor = {
> > { .dt_id = MT8192_AP_INFRA },
> > { .dt_id = MT8192_AP_CAM },
> > @@ -1326,7 +1326,7 @@ static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
> > .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
> > },
> > {
> > - .cal_offset = { 0x40, 0x43, 0x46 },
> > + .cal_offset = { 0x3c, 0x40, 0x44 },
> > .lvts_sensor = {
> > { .dt_id = MT8192_AP_MD0 },
> > { .dt_id = MT8192_AP_MD1 },
> > --
> > 2.40.0
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