linux-kernel - Re: [EXTERNAL] Re: [PATCH v14 4/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0

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Message-ID: <b66ea55a-fc9a-8a3f-5b06-247769c50087@ti.com>
Date:   Tue, 25 Apr 2023 17:46:18 +0530
From:   Ravi Gunasekaran <r-gunasekaran@...com>
To:     Roger Quadros <rogerq@...nel.org>, <nm@...com>, <afd@...com>,
        <vigneshr@...com>, <kristo@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <s-vadapalli@...com>,
        <vaishnav.a@...com>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [EXTERNAL] Re: [PATCH v14 4/8] arm64: dts: ti:
 k3-j721s2-common-proc-board: Enable SERDES0

Roger,

On 25/04/23 5:15 pm, Roger Quadros wrote:
> Hi,
> 
> On 31/03/2023 12:00, Ravi Gunasekaran wrote:
>> From: Aswath Govindraju <a-govindraju@...com>
>>
>> Configure first lane to PCIe, the second lane to USB and the last two lanes
>> to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is
>> connected to PCIe.
> 
> Is USB0 expected to work in super-speed on this board?
> If yes then you need to add USB0 lane information as well.
> Otherwise please ignore my comment.
> 

The SerDes on J721S2 can simultaneously support only two protocols.
By default PCIe and DP will be supported. Due to this, USB is configured
in high-speed and this does not require any SerDes lane configuration.

>>
>> Signed-off-by: Aswath Govindraju <a-govindraju@...com>
>> Signed-off-by: Matt Ranostay <mranostay@...com>
>> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@...com>

[...]

> 
> cheers,
> -roger

-- 
Regards,
Ravi