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Message-Id: <20230411-dpu-intf-te-v4-9-27ce1a5ab5c6@somainline.org>
Date: Thu, 27 Apr 2023 00:37:23 +0200
From: Marijn Suijten <marijn.suijten@...ainline.org>
To: Rob Clark <robdclark@...il.com>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Sean Paul <sean@...rly.run>, David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Adam Skladowski <a39.skl@...il.com>,
Loic Poulain <loic.poulain@...aro.org>,
Bjorn Andersson <andersson@...nel.org>,
Kuogee Hsieh <quic_khsieh@...cinc.com>,
Robert Foss <rfoss@...nel.org>, Vinod Koul <vkoul@...nel.org>,
Neil Armstrong <neil.armstrong@...aro.org>
Cc: ~postmarketos/upstreaming@...ts.sr.ht,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...ainline.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Martin Botka <martin.botka@...ainline.org>,
Jami Kettunen <jami.kettunen@...ainline.org>,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
Jordan Crouse <jordan@...micpenguin.net>,
Jessica Zhang <quic_jesszhan@...cinc.com>,
Marijn Suijten <marijn.suijten@...ainline.org>
Subject: [PATCH v4 09/22] drm/msm/dpu: Remove extraneous register define
indentation
A bunch of registers are indented with two extra spaces, looking as if
these are values corresponding to the previous register which is not the
case, rather these are simply also register offsets and should only have
a single space separating them and the #define keyword.
Signed-off-by: Marijn Suijten <marijn.suijten@...ainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@...cinc.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 41 +++++++++++++++--------------
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index b9dddf576c029..1d22d7dc99b86 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -38,26 +38,27 @@
#define INTF_ACTIVE_DATA_HCTL 0x068
#define INTF_FRAME_LINE_COUNT_EN 0x0A8
#define INTF_FRAME_COUNT 0x0AC
-#define INTF_LINE_COUNT 0x0B0
-
-#define INTF_DEFLICKER_CONFIG 0x0F0
-#define INTF_DEFLICKER_STRNG_COEFF 0x0F4
-#define INTF_DEFLICKER_WEAK_COEFF 0x0F8
-
-#define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084
-#define INTF_PANEL_FORMAT 0x090
-#define INTF_TPG_ENABLE 0x100
-#define INTF_TPG_MAIN_CONTROL 0x104
-#define INTF_TPG_VIDEO_CONFIG 0x108
-#define INTF_TPG_COMPONENT_LIMITS 0x10C
-#define INTF_TPG_RECTANGLE 0x110
-#define INTF_TPG_INITIAL_VALUE 0x114
-#define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118
-#define INTF_TPG_RGB_MAPPING 0x11C
-#define INTF_PROG_FETCH_START 0x170
-#define INTF_PROG_ROT_START 0x174
-#define INTF_MUX 0x25C
-#define INTF_STATUS 0x26C
+#define INTF_LINE_COUNT 0x0B0
+
+#define INTF_DEFLICKER_CONFIG 0x0F0
+#define INTF_DEFLICKER_STRNG_COEFF 0x0F4
+#define INTF_DEFLICKER_WEAK_COEFF 0x0F8
+
+#define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084
+#define INTF_PANEL_FORMAT 0x090
+#define INTF_TPG_ENABLE 0x100
+#define INTF_TPG_MAIN_CONTROL 0x104
+#define INTF_TPG_VIDEO_CONFIG 0x108
+#define INTF_TPG_COMPONENT_LIMITS 0x10C
+#define INTF_TPG_RECTANGLE 0x110
+#define INTF_TPG_INITIAL_VALUE 0x114
+#define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118
+#define INTF_TPG_RGB_MAPPING 0x11C
+#define INTF_PROG_FETCH_START 0x170
+#define INTF_PROG_ROT_START 0x174
+
+#define INTF_MUX 0x25C
+#define INTF_STATUS 0x26C
#define INTF_CFG_ACTIVE_H_EN BIT(29)
#define INTF_CFG_ACTIVE_V_EN BIT(30)
--
2.40.1
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