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Message-ID: <79a8726f-534c-ea2d-f029-7c3e9256fc54@linaro.org>
Date: Wed, 26 Apr 2023 10:17:32 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Marijn Suijten <marijn.suijten@...ainline.org>
Cc: Rob Clark <robdclark@...il.com>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Sean Paul <sean@...rly.run>, David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Adam Skladowski <a39.skl@...il.com>,
Loic Poulain <loic.poulain@...aro.org>,
Bjorn Andersson <andersson@...nel.org>,
Kuogee Hsieh <quic_khsieh@...cinc.com>,
Robert Foss <rfoss@...nel.org>, Vinod Koul <vkoul@...nel.org>,
Neil Armstrong <neil.armstrong@...aro.org>,
~postmarketos/upstreaming@...ts.sr.ht,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...ainline.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Martin Botka <martin.botka@...ainline.org>,
Jami Kettunen <jami.kettunen@...ainline.org>,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
Jordan Crouse <jordan@...micpenguin.net>,
Jessica Zhang <quic_jesszhan@...cinc.com>
Subject: Re: [PATCH v3 17/21] drm/msm/dpu: Describe TEAR interrupt registers
for DSI interfaces
On 26/04/2023 10:16, Marijn Suijten wrote:
> On 2023-04-26 03:05:12, Dmitry Baryshkov wrote:
>> On 26/04/2023 02:06, Marijn Suijten wrote:
>>> All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of
>>> the PINGPONG block and into the INTF block. Wire up the IRQ register
>>> masks in the interrupt table for enabling, reading and clearing them.
>>>
>>> Signed-off-by: Marijn Suijten <marijn.suijten@...ainline.org>
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 52 +++++++++++++++++------
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 4 ++
>>> 2 files changed, 44 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
>>> index e116993b2f8f7..5e2d68ebb113e 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
>>> @@ -17,18 +17,26 @@
>>> * Register offsets in MDSS register file for the interrupt registers
>>> * w.r.t. the MDP base
>>> */
>>> -#define MDP_INTF_OFF(intf) (0x6A000 + 0x800 * (intf))
>>> -#define MDP_INTF_INTR_EN(intf) (MDP_INTF_OFF(intf) + 0x1c0)
>>> -#define MDP_INTF_INTR_STATUS(intf) (MDP_INTF_OFF(intf) + 0x1c4)
>>> -#define MDP_INTF_INTR_CLEAR(intf) (MDP_INTF_OFF(intf) + 0x1c8)
>>> -#define MDP_AD4_OFF(ad4) (0x7C000 + 0x1000 * (ad4))
>>> -#define MDP_AD4_INTR_EN_OFF(ad4) (MDP_AD4_OFF(ad4) + 0x41c)
>>> -#define MDP_AD4_INTR_CLEAR_OFF(ad4) (MDP_AD4_OFF(ad4) + 0x424)
>>> -#define MDP_AD4_INTR_STATUS_OFF(ad4) (MDP_AD4_OFF(ad4) + 0x420)
>>> -#define MDP_INTF_REV_7xxx_OFF(intf) (0x34000 + 0x1000 * (intf))
>>> -#define MDP_INTF_REV_7xxx_INTR_EN(intf) (MDP_INTF_REV_7xxx_OFF(intf) + 0x1c0)
>>> -#define MDP_INTF_REV_7xxx_INTR_STATUS(intf) (MDP_INTF_REV_7xxx_OFF(intf) + 0x1c4)
>>> -#define MDP_INTF_REV_7xxx_INTR_CLEAR(intf) (MDP_INTF_REV_7xxx_OFF(intf) + 0x1c8)
>>> +#define MDP_INTF_OFF(intf) (0x6A000 + 0x800 * (intf))
>>> +#define MDP_INTF_INTR_EN(intf) (MDP_INTF_OFF(intf) + 0x1c0)
>>> +#define MDP_INTF_INTR_STATUS(intf) (MDP_INTF_OFF(intf) + 0x1c4)
>>> +#define MDP_INTF_INTR_CLEAR(intf) (MDP_INTF_OFF(intf) + 0x1c8)
>>> +#define MDP_INTF_TEAR_OFF(intf) (0x6D700 + 0x100 * (intf))
>>> +#define MDP_INTF_INTR_TEAR_EN(intf) (MDP_INTF_TEAR_OFF(intf) + 0x000)
>>> +#define MDP_INTF_INTR_TEAR_STATUS(intf) (MDP_INTF_TEAR_OFF(intf) + 0x004)
>>> +#define MDP_INTF_INTR_TEAR_CLEAR(intf) (MDP_INTF_TEAR_OFF(intf) + 0x008)
>>> +#define MDP_AD4_OFF(ad4) (0x7C000 + 0x1000 * (ad4))
>>> +#define MDP_AD4_INTR_EN_OFF(ad4) (MDP_AD4_OFF(ad4) + 0x41c)
>>> +#define MDP_AD4_INTR_CLEAR_OFF(ad4) (MDP_AD4_OFF(ad4) + 0x424)
>>> +#define MDP_AD4_INTR_STATUS_OFF(ad4) (MDP_AD4_OFF(ad4) + 0x420)
>>
>>
>> Please don't reindent lines together with doing the actual changes.
>> Please set the correct alignment in the patch 10
>
> The alignment here is extended to accomodate for
> MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(intf), or do you want me to reserve
> the right indentation from the get-go in patch 10? That'd certainly
> make it more clear which lines are added here, and patch 10 already
> adjusts the alignment anyway.
Yes, please.
>
> - Marijn
>
>>> +#define MDP_INTF_REV_7xxx_OFF(intf) (0x34000 + 0x1000 * (intf))
>>> +#define MDP_INTF_REV_7xxx_INTR_EN(intf) (MDP_INTF_REV_7xxx_OFF(intf) + 0x1c0)
>>> +#define MDP_INTF_REV_7xxx_INTR_STATUS(intf) (MDP_INTF_REV_7xxx_OFF(intf) + 0x1c4)
>>> +#define MDP_INTF_REV_7xxx_INTR_CLEAR(intf) (MDP_INTF_REV_7xxx_OFF(intf) + 0x1c8)
>>> +#define MDP_INTF_REV_7xxx_TEAR_OFF(intf) (0x34800 + 0x1000 * (intf))
>>> +#define MDP_INTF_REV_7xxx_INTR_TEAR_EN(intf) (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x000)
>>> +#define MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x004)
>>> +#define MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x008)
>>>
>>> /**
>>> * struct dpu_intr_reg - array of DPU register sets
>>> @@ -93,6 +101,16 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
>>> MDP_INTF_INTR_EN(5),
>>> MDP_INTF_INTR_STATUS(5)
>>> },
>>> + [MDP_INTF1_TEAR_INTR] = {
>>> + MDP_INTF_INTR_TEAR_CLEAR(1),
>>> + MDP_INTF_INTR_TEAR_EN(1),
>>> + MDP_INTF_INTR_TEAR_STATUS(1)
>>> + },
>>> + [MDP_INTF2_TEAR_INTR] = {
>>> + MDP_INTF_INTR_TEAR_CLEAR(2),
>>> + MDP_INTF_INTR_TEAR_EN(2),
>>> + MDP_INTF_INTR_TEAR_STATUS(2)
>>> + },
>>> [MDP_AD4_0_INTR] = {
>>> MDP_AD4_INTR_CLEAR_OFF(0),
>>> MDP_AD4_INTR_EN_OFF(0),
>>> @@ -113,11 +131,21 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
>>> MDP_INTF_REV_7xxx_INTR_EN(1),
>>> MDP_INTF_REV_7xxx_INTR_STATUS(1)
>>> },
>>> + [MDP_INTF1_7xxx_TEAR_INTR] = {
>>> + MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1),
>>> + MDP_INTF_REV_7xxx_INTR_TEAR_EN(1),
>>> + MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1)
>>> + },
>>> [MDP_INTF2_7xxx_INTR] = {
>>> MDP_INTF_REV_7xxx_INTR_CLEAR(2),
>>> MDP_INTF_REV_7xxx_INTR_EN(2),
>>> MDP_INTF_REV_7xxx_INTR_STATUS(2)
>>> },
>>> + [MDP_INTF2_7xxx_TEAR_INTR] = {
>>> + MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2),
>>> + MDP_INTF_REV_7xxx_INTR_TEAR_EN(2),
>>> + MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2)
>>> + },
>>> [MDP_INTF3_7xxx_INTR] = {
>>> MDP_INTF_REV_7xxx_INTR_CLEAR(3),
>>> MDP_INTF_REV_7xxx_INTR_EN(3),
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
>>> index 425465011c807..fda7f8c9caece 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
>>> @@ -23,11 +23,15 @@ enum dpu_hw_intr_reg {
>>> MDP_INTF3_INTR,
>>> MDP_INTF4_INTR,
>>> MDP_INTF5_INTR,
>>> + MDP_INTF1_TEAR_INTR,
>>> + MDP_INTF2_TEAR_INTR,
>>> MDP_AD4_0_INTR,
>>> MDP_AD4_1_INTR,
>>> MDP_INTF0_7xxx_INTR,
>>> MDP_INTF1_7xxx_INTR,
>>> + MDP_INTF1_7xxx_TEAR_INTR,
>>> MDP_INTF2_7xxx_INTR,
>>> + MDP_INTF2_7xxx_TEAR_INTR,
>>> MDP_INTF3_7xxx_INTR,
>>> MDP_INTF4_7xxx_INTR,
>>> MDP_INTF5_7xxx_INTR,
>>>
>>
>> --
>> With best wishes
>> Dmitry
>>
--
With best wishes
Dmitry
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