lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-Id: <20230427055032.85015-1-rath@ibv-augsburg.de>
Date:   Thu, 27 Apr 2023 07:50:29 +0200
From:   Dominic Rath <rath@...-augsburg.de>
To:     robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        tjoseph@...ence.com
Cc:     bhelgaas@...gle.com, lpieralisi@...nel.org, nm@...com,
        vigneshr@...com, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
        christian.gmeiner@...il.com, bahle@...-augsburg.de,
        Dominic Rath <rath@...-augsburg.de>
Subject: [PATCH v2 0/3] Cadence PCIe PHY latency for PTM

Hello Everyone,

this series adds PHY latency properties to the Cadence PCIe
driver to improve PTM accuracy, and configures the necessary
values for TI's AM64x processors.

These latencies are implementation specific and need to be
configured in the PCIe IP core's registers to allow the
PCIe controller to exactly determine the RX/TX timestamps for
PCIe PTM messages.

TI doesn't document these values in the datasheet or reference
manual as of now, but provided the necessary data via TI's E2E
forums (see PATCH 3/3).

Changes from v1 to v2:
   - move latency property to PHY instead of PCIe controller
   - drop vendor prefix from property name
   - rephrase commit message regarding optional properties
   - emit an info message instead of a warning in case
     an optional property is missing

Best Regards,

Dominic

Alexander Bahle (3):
  dt-bindings: phy: cadence-torrent: Add latency properties
  PCI: cadence: Use DT bindings to set PHY latencies
  arm64: dts: ti: k3-am64: Add PCIe PHY latency DT binding

 .../bindings/phy/phy-cadence-torrent.yaml     | 20 ++++
 arch/arm64/boot/dts/ti/k3-am642-evm.dts       |  2 +
 .../pci/controller/cadence/pcie-cadence-ep.c  |  2 +
 .../controller/cadence/pcie-cadence-host.c    |  1 +
 drivers/pci/controller/cadence/pcie-cadence.c | 92 +++++++++++++++++++
 drivers/pci/controller/cadence/pcie-cadence.h | 23 +++++
 6 files changed, 140 insertions(+)


base-commit: 0cfd8703e7da687924371e9bc77a025bdeba9637
-- 
2.36.0

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ