linux-kernel - Re: [PATCH v3 03/46] perf stat: Introduce skippable evsels

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Date:   Mon, 1 May 2023 16:25:35 -0400
From:   "Liang, Kan" <kan.liang@...ux.intel.com>
To:     Ian Rogers <irogers@...gle.com>,
        Weilin Wang <weilin.wang@...el.com>
Cc:     Arnaldo Carvalho de Melo <acme@...nel.org>,
        Ahmad Yasin <ahmad.yasin@...el.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Stephane Eranian <eranian@...gle.com>,
        Andi Kleen <ak@...ux.intel.com>,
        Perry Taylor <perry.taylor@...el.com>,
        Samantha Alt <samantha.alt@...el.com>,
        Caleb Biggers <caleb.biggers@...el.com>,
        Edward Baker <edward.baker@...el.com>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Florian Fischer <florian.fischer@...q.space>,
        Rob Herring <robh@...nel.org>,
        Zhengjun Xing <zhengjun.xing@...ux.intel.com>,
        John Garry <john.g.garry@...cle.com>,
        Kajol Jain <kjain@...ux.ibm.com>,
        Sumanth Korikkar <sumanthk@...ux.ibm.com>,
        Thomas Richter <tmricht@...ux.ibm.com>,
        Tiezhu Yang <yangtiezhu@...ngson.cn>,
        Ravi Bangoria <ravi.bangoria@....com>,
        Leo Yan <leo.yan@...aro.org>,
        Yang Jihong <yangjihong1@...wei.com>,
        James Clark <james.clark@....com>,
        Suzuki Poulouse <suzuki.poulose@....com>,
        Kang Minchul <tegongkang@...il.com>,
        Athira Rajeev <atrajeev@...ux.vnet.ibm.com>,
        linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 03/46] perf stat: Introduce skippable evsels



On 2023-05-01 11:29 a.m., Ian Rogers wrote:
> The events are displayed twice as there are 2 groups of events. This
> is changed by:
> https://lore.kernel.org/lkml/20230429053506.1962559-5-irogers@google.com/
> where the events are no longer grouped.

The trick seems don't work on a hybrid machine. I still got the
duplicate Topdown events on e-core.


         38,841.16 msec cpu-clock                        #   32.009 CPUs
utilized
               256      context-switches                 #    6.591 /sec
                33      cpu-migrations                   #    0.850 /sec
                84      page-faults                      #    2.163 /sec
        21,910,584      cpu_core/cycles/                 #  564.107 K/sec
       248,153,249      cpu_atom/cycles/                 #    6.389
M/sec                       (53.85%)
        27,463,908      cpu_core/instructions/           #  707.083 K/sec
       118,661,014      cpu_atom/instructions/           #    3.055
M/sec                       (63.06%)
         4,652,941      cpu_core/branches/               #  119.794 K/sec
        20,173,082      cpu_atom/branches/               #  519.374
K/sec                       (63.18%)
            72,727      cpu_core/branch-misses/          #    1.872 K/sec
         1,143,187      cpu_atom/branch-misses/          #   29.432
K/sec                       (63.51%)
       125,630,586      cpu_core/TOPDOWN.SLOTS/          #      nan %
tma_backend_bound
                                                  #      nan %  tma_retiring
                                                  #      0.0 %
tma_bad_speculation
                                                  #      nan %
tma_frontend_bound
        30,254,701      cpu_core/topdown-retiring/
       149,075,726      cpu_atom/TOPDOWN_RETIRING.ALL/   #    3.838 M/sec
                                                  #     14.8 %
tma_bad_speculation      (63.82%)
   <not supported>      cpu_core/topdown-bad-spec/
       523,614,383      cpu_atom/TOPDOWN_FE_BOUND.ALL/   #   13.481 M/sec
                                                  #     42.0 %
tma_frontend_bound       (64.15%)
       385,502,477      cpu_atom/TOPDOWN_BE_BOUND.ALL/   #    9.925 M/sec
                                                  #     30.9 %
tma_backend_bound
                                                  #     30.9 %
tma_backend_bound_aux    (64.39%)
       249,534,488      cpu_atom/CPU_CLK_UNHALTED.CORE/  #    6.424 M/sec
                                                  #     12.2 %
tma_retiring             (64.18%)
       151,729,465      cpu_atom/TOPDOWN_RETIRING.ALL/   #    3.906
M/sec                       (54.67%)
       530,621,769      cpu_atom/TOPDOWN_FE_BOUND.ALL/   #   13.661
M/sec                       (54.30%)
   <not supported>      cpu_core/topdown-fe-bound/
       383,694,745      cpu_atom/TOPDOWN_BE_BOUND.ALL/   #    9.879
M/sec                       (53.96%)
   <not supported>      cpu_core/topdown-be-bound/
           105,850      cpu_core/INT_MISC.UOP_DROPPING/  #    2.725 K/sec

       1.213449538 seconds time elapsed

Thanks,
Kan