| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20230430-riscv-cbqri-rfc-v2-v2-2-8e3725c4a473@baylibre.com>
Date: Mon, 01 May 2023 14:05:22 -0700
From: Drew Fustini <dfustini@...libre.com>
To: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Ved Shanbhogue <ved@...osinc.com>,
Atish Patra <atishp@...osinc.com>,
Björn Töpel <bjorn@...osinc.com>,
James Morse <james.morse@....com>,
Kornel Dulęba <mindal@...ihalf.com>,
Adrien Ricciardi <aricciardi@...libre.com>,
Drew Fustini <dfustini@...libre.com>
Subject: [PATCH RFC v2 2/2] RISC-V: Add support for sqoscfg CSR
Add support for the sqoscfg CSR defined in the Ssqosid ISA extension
(Supervisor-mode Quality of Service ID). The CSR contains two fields:
- Resource Control ID (RCID) used determine resource allocation
- Monitoring Counter ID (MCID) used to track resource usage
Requests from a hart to shared resources like cache will be tagged with
these IDs. This allows the usage of shared resources to be associated
with the task currently running on the hart.
A sqoscfg field is added to thread_struct and has the same format as the
sqoscfg CSR. This allows the scheduler to set the hart's sqoscfg CSR to
contain the RCID and MCID for the task that is being scheduled in. The
sqoscfg CSR is only written to if the thread_struct.sqoscfg is different
from the current value of the CSR.
A per-cpu variable cpu_sqoscfg is used to mirror that state of the CSR.
This is because access to L1D hot memory should be several times faster
than a CSR read. Also, in the case of virtualization, accesses to this
CSR are trapped in the hypervisor.
Link: https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf
Co-developed-by: Kornel Dulęba <mindal@...ihalf.com>
Signed-off-by: Kornel Dulęba <mindal@...ihalf.com>
Signed-off-by: Drew Fustini <dfustini@...libre.com>
---
arch/riscv/Kconfig | 19 +++++++++++++++++
arch/riscv/include/asm/csr.h | 8 +++++++
arch/riscv/include/asm/processor.h | 3 +++
arch/riscv/include/asm/qos.h | 43 ++++++++++++++++++++++++++++++++++++++
arch/riscv/include/asm/switch_to.h | 3 +++
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/qos/Makefile | 2 ++
arch/riscv/kernel/qos/qos.c | 5 +++++
8 files changed, 84 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c58d74235363..4de2ce69f9fa 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -409,6 +409,25 @@ config RISCV_ISA_C
If you don't know what to do here, say Y.
+config RISCV_ISA_SSQOSID
+ bool "Ssqosid extension support for supervisor mode QoS ID"
+ default y
+ help
+ Adds support for the Ssqosid ISA extension (Supervisor-mode
+ Quality of Service ID).
+
+ Ssqosid defines the sqoscfg CSR which allows the system to tag
+ the running process with RCID (Resource Control ID) and MCID
+ (Monitoring Counter ID). The RCID is used determine resource
+ allocation. The MCID is used to track resource usage in event
+ counters.
+
+ For example, a cache controller may use the RCID to apply a
+ cache partitioning scheme and use the MCID to track how much
+ cache a process, or a group of processes, is using.
+
+ If you don't know what to do here, say Y.
+
config RISCV_ISA_SVNAPOT
bool "Svnapot extension support for supervisor mode NAPOT pages"
depends on 64BIT && MMU
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 7c2b8cdb7b77..17d04a0cacd6 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -59,6 +59,13 @@
#define SATP_ASID_MASK _AC(0xFFFF, UL)
#endif
+/* SQOSCFG fields */
+#define SQOSCFG_RCID_MASK _AC(0x00000FFF, UL)
+#define SQOSCFG_MCID_MASK SQOSCFG_RCID_MASK
+#define SQOSCFG_MCID_SHIFT 16
+#define SQOSCFG_MASK ((SQOSCFG_MCID_MASK << SQOSCFG_MCID_SHIFT) | \
+ SQOSCFG_RCID_MASK)
+
/* Exception cause high bit - is an interrupt if set */
#define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
@@ -245,6 +252,7 @@
#define CSR_STVAL 0x143
#define CSR_SIP 0x144
#define CSR_SATP 0x180
+#define CSR_SQOSCFG 0x181
#define CSR_STIMECMP 0x14D
#define CSR_STIMECMPH 0x15D
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index 94a0590c6971..724b2aa2732d 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -39,6 +39,9 @@ struct thread_struct {
unsigned long s[12]; /* s[0]: frame pointer */
struct __riscv_d_ext_state fstate;
unsigned long bad_cause;
+#ifdef CONFIG_RISCV_ISA_SSQOSID
+ u32 sqoscfg;
+#endif
};
/* Whitelist the fstate from the task_struct for hardened usercopy */
diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h
new file mode 100644
index 000000000000..9d0fe1ac1b34
--- /dev/null
+++ b/arch/riscv/include/asm/qos.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_RISCV_QOS_H
+#define _ASM_RISCV_QOS_H
+
+#ifdef CONFIG_RISCV_ISA_SSQOSID
+
+#include <linux/sched.h>
+#include <linux/jump_label.h>
+
+#include <asm/barrier.h>
+#include <asm/csr.h>
+#include <asm/hwcap.h>
+
+/* cached value of sqoscfg csr for each cpu */
+DECLARE_PER_CPU(u32, cpu_sqoscfg);
+
+static inline void __switch_to_sqoscfg(struct task_struct *prev,
+ struct task_struct *next)
+{
+ u32 *cpu_sqoscfg_ptr = this_cpu_ptr(&cpu_sqoscfg);
+ u32 thread_sqoscfg;
+
+ thread_sqoscfg = READ_ONCE(next->thread.sqoscfg);
+
+ if (thread_sqoscfg != *cpu_sqoscfg_ptr) {
+ *cpu_sqoscfg_ptr = thread_sqoscfg;
+ csr_write(CSR_SQOSCFG, thread_sqoscfg);
+ }
+}
+
+static __always_inline bool has_sqoscfg(void)
+{
+ return riscv_has_extension_likely(RISCV_ISA_EXT_SSQOSID);
+}
+
+#else /* ! CONFIG_RISCV_ISA_SSQOSID */
+
+static __always_inline bool has_sqoscfg(void) { return false; }
+#define __switch_to_sqoscfg(__prev, __next) do { } while (0)
+
+#endif /* CONFIG_RISCV_ISA_SSQOSID */
+
+#endif /* _ASM_RISCV_QOS_H */
diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 60f8ca01d36e..79e8e907d7a6 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -12,6 +12,7 @@
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/csr.h>
+#include <asm/qos.h>
#ifdef CONFIG_FPU
extern void __fstate_save(struct task_struct *save_to);
@@ -78,6 +79,8 @@ do { \
struct task_struct *__next = (next); \
if (has_fpu()) \
__switch_to_aux(__prev, __next); \
+ if (has_sqoscfg()) \
+ __switch_to_sqoscfg(__prev, __next); \
((last) = __switch_to(__prev, __next)); \
} while (0)
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index 0fee73a20c87..22c18b916212 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -89,3 +89,4 @@ obj-$(CONFIG_COMPAT) += compat_signal.o
obj-$(CONFIG_COMPAT) += compat_vdso/
obj-$(CONFIG_64BIT) += pi/
+obj-$(CONFIG_RISCV_ISA_SSQOSID) += qos/
diff --git a/arch/riscv/kernel/qos/Makefile b/arch/riscv/kernel/qos/Makefile
new file mode 100644
index 000000000000..9f996263a86d
--- /dev/null
+++ b/arch/riscv/kernel/qos/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_RISCV_ISA_SSQOSID) += qos.o
diff --git a/arch/riscv/kernel/qos/qos.c b/arch/riscv/kernel/qos/qos.c
new file mode 100644
index 000000000000..a6956664dfe1
--- /dev/null
+++ b/arch/riscv/kernel/qos/qos.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <asm/qos.h>
+
+/* cached value of sqoscfg csr for each cpu */
+DEFINE_PER_CPU(u32, cpu_sqoscfg);
--
2.34.1
Powered by blists - more mailing lists