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Message-ID: <ca4da3c1-29dd-6d7d-6fe6-dd6ecc7fff88@quicinc.com>
Date: Tue, 2 May 2023 14:07:17 +0530
From: Krishna Kurapati PSSNV <quic_kriskura@...cinc.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Andy Gross <agross@...nel.org>,
"Bjorn Andersson" <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Felipe Balbi <balbi@...nel.org>,
"Wesley Cheng" <quic_wcheng@...cinc.com>
CC: <linux-usb@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<quic_pkondeti@...cinc.com>, <quic_ppratap@...cinc.com>,
<quic_jackp@...cinc.com>, <quic_harshq@...cinc.com>,
<ahalaney@...hat.com>, <quic_shazhuss@...cinc.com>
Subject: Re: [PATCH v7 7/9] arm64: dts: qcom: sc8280xp: Add multiport
controller node for SC8280
On 5/2/2023 1:17 PM, Krzysztof Kozlowski wrote:
> On 01/05/2023 16:34, Krishna Kurapati wrote:
>> Add USB and DWC3 node for tertiary port of SC8280 along with multiport
>> IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride
>> platforms.
>>
>> Signed-off-by: Krishna Kurapati <quic_kriskura@...cinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 64 ++++++++++++++++++++++++++
>> 1 file changed, 64 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> index 8fa9fbfe5d00..0e4fb286956b 100644
>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> @@ -3133,6 +3133,70 @@ usb_1_role_switch: endpoint {
>> };
>> };
>>
>> + usb_2: usb@...8800 {
>
> Nodes are ordered by unit address, more or less >
>> + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
>> + reg = <0 0x0a4f8800 0 0x400>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
>> + <&gcc GCC_USB30_MP_MASTER_CLK>,
>> + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
>> + <&gcc GCC_USB30_MP_SLEEP_CLK>,
>> + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
>> + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
>> + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
>> + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
>> + <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
>> + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
>> + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
>> +
>> + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
>> + <&gcc GCC_USB30_MP_MASTER_CLK>;
>> + assigned-clock-rates = <19200000>, <200000000>;
>> +
>> + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
>> + <&pdc 126 IRQ_TYPE_EDGE_RISING>,
>> + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
>
> Does not look aligned. >
>> +
>> + interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq",
>> + "ss_phy_irq", "pwr_event_1",
>
> Does not look aligned.
>
Sure, will fix up the indentation issues.
>> + "pwr_event_2", "pwr_event_3",
>> + "pwr_event_4";
>> +
>> + power-domains = <&gcc USB30_MP_GDSC>;
>> +
>> + resets = <&gcc GCC_USB30_MP_BCR>;
>> +
>> + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
>> + interconnect-names = "usb-ddr", "apps-usb";
>> +
>> + required-opps = <&rpmhpd_opp_nom>;
>> +
>
> Please open the DTSI and look how this is organized there. I don't think
> doing this differently - with different order - helps to review.
> required-opps is next to power-domains.
Sure. Will fix it up.
>
>> + status = "disabled";
>> +
>> + usb_2_dwc3: usb@...0000 {
>> + compatible = "snps,dwc3";
>> + reg = <0 0x0a400000 0 0xcd00>;
>> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>> + iommus = <&apps_smmu 0x800 0x0>;
>> + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>,
>> + <&usb_2_hsphy1>, <&usb_2_qmpphy1>,
>> + <&usb_2_hsphy2>,
>> + <&usb_2_hsphy3>;
>> + phy-names = "usb2-port0", "usb3-port0",
>> + "usb2-port1", "usb3-port1",
>> + "usb2-port2",
>> + "usb2-port3";
>> + };
>> + };
>> +
>> mdss0: display-subsystem@...0000 {
>> compatible = "qcom,sc8280xp-mdss";
>> reg = <0 0x0ae00000 0 0x1000>;
>
Thanks,
Krishna,
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