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Message-ID: <cf4ced33cb7dc8d43b79bb9d4ad6acd3b8ecc09b.1683034376.git.michal.simek@amd.com>
Date: Tue, 2 May 2023 15:35:33 +0200
From: Michal Simek <michal.simek@....com>
To: <linux-kernel@...r.kernel.org>, <monstr@...str.eu>,
<michal.simek@...inx.com>, <git@...inx.com>
CC: Radhey Shyam Pandey <radhey.shyam.pandey@....com>,
Harini Katakam <harini.katakam@....com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Michael Grzeschik <m.grzeschik@...gutronix.de>,
Rob Herring <robh+dt@...nel.org>,
Robert Hancock <robert.hancock@...ian.com>,
Tanmay Shah <tanmay.shah@....com>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
Subject: [PATCH 05/23] arm64: zynqmp: Add L2 cache nodes
From: Radhey Shyam Pandey <radhey.shyam.pandey@....com>
Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for
CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache
node and let each CPU point to it.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@....com>
Signed-off-by: Michal Simek <michal.simek@....com>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index bb0d0be30aa0..c2d80c7967e9 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -33,6 +33,7 @@ cpu0: cpu@0 {
operating-points-v2 = <&cpu_opp_table>;
reg = <0x0>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2>;
};
cpu1: cpu@1 {
@@ -42,6 +43,7 @@ cpu1: cpu@1 {
reg = <0x1>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2>;
};
cpu2: cpu@2 {
@@ -51,6 +53,7 @@ cpu2: cpu@2 {
reg = <0x2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2>;
};
cpu3: cpu@3 {
@@ -60,6 +63,12 @@ cpu3: cpu@3 {
reg = <0x3>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2>;
+ };
+
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
};
idle-states {
--
2.36.1
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