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Message-ID: <CAP-5=fWY2SYdiogQoxEkAMAc8+_S5Mt3PgO1_=AhbKY3aicgYg@mail.gmail.com>
Date: Tue, 2 May 2023 09:19:32 -0700
From: Ian Rogers <irogers@...gle.com>
To: Ravi Bangoria <ravi.bangoria@....com>
Cc: Arnaldo Carvalho de Melo <acme@...nel.org>,
Kan Liang <kan.liang@...ux.intel.com>,
Ahmad Yasin <ahmad.yasin@...el.com>,
Peter Zijlstra <peterz@...radead.org>,
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Andi Kleen <ak@...ux.intel.com>,
Perry Taylor <perry.taylor@...el.com>,
Samantha Alt <samantha.alt@...el.com>,
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Weilin Wang <weilin.wang@...el.com>,
Edward Baker <edward.baker@...el.com>,
Mark Rutland <mark.rutland@....com>,
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Jiri Olsa <jolsa@...nel.org>,
Namhyung Kim <namhyung@...nel.org>,
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linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 14/46] perf test: Mask config then test
On Tue, May 2, 2023 at 3:44 AM Ravi Bangoria <ravi.bangoria@....com> wrote:
>
> > @@ -87,7 +92,7 @@ static int test__checkevent_raw(struct evlist *evlist)
> >
> > TEST_ASSERT_VAL("wrong number of entries", 1 == evlist->core.nr_entries);
> > TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW == evsel->core.attr.type);
> > - TEST_ASSERT_VAL("wrong config", 0x1a == evsel->core.attr.config);
> > + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a));
>
> Extended 'type' via 'config' is applicable only to HW and HW_CACHE types.
> I think we should not apply test_config() for other types. Even if they
> are ineffective in these tests (because we are not setting upper bits),
> they are semantically wrong IMO.
>
> In fact, AMD EventSelect is 12 bits and upper 4 bits are located at 35:32
> in PerfEvtSel register. So for RAW events, upper bits MUST NOT be ignored.
Thanks Ravi, this is important and I'll update the tests as you
suggest. I'd been iterating on this, which is why the test is this
way. We have two parsing cases, one where the type is explicitly given
like:
$ perf stat -e '4:0xC0' true
and another where the raw config is wildcard applied like:
$ perf stat -e 'rC0' true
The question is which PMUs should the 0xC0 raw event be opened on? The
answer in the code is to ignore all PMUs that aren't the "core" PMUs,
so cpu, cpu_atom, cpu_core, armv8... This matches existing behavior
but it wasn't clear to me that this was intentional. I think in the
future the wildcard application can be made more efficient to ignore
unnecessary PMUs and avoid the sysfs scan. Something that is a bit of
an issue in the event parsing is what exactly should be applied by
wildcard matching and there are inconsistencies.
Thanks,
Ian
> > @@ -139,8 +142,7 @@ static int test__checkevent_symbolic_alias(struct evlist *evlist)
> >
> > TEST_ASSERT_VAL("wrong number of entries", 1 == evlist->core.nr_entries);
> > TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE == evsel->core.attr.type);
> > - TEST_ASSERT_VAL("wrong config",
> > - PERF_COUNT_SW_PAGE_FAULTS == evsel->core.attr.config);
> > + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_SW_PAGE_FAULTS));
>
> Ditto for PERF_TYPE_SOFTWARE. We should not use test_config().
>
>
> > @@ -160,7 +162,7 @@ static int test__checkevent_breakpoint(struct evlist *evlist)
> >
> > TEST_ASSERT_VAL("wrong number of entries", 1 == evlist->core.nr_entries);
> > TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT == evsel->core.attr.type);
> > - TEST_ASSERT_VAL("wrong config", 0 == evsel->core.attr.config);
> > + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0));
>
> Ditto for PERF_TYPE_BREAKPOINT.
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