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Message-ID: <CAOX2RU5WYm-wJXByAx8yavDPhR1=2MHjj0Kh1z6h_EHhS8DVGw@mail.gmail.com>
Date: Wed, 3 May 2023 21:56:53 +0200
From: Robert Marko <robimarko@...il.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc: agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: ipq8074: Add QUP5 SPI node
On Mon, 1 May 2023 at 12:03, Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org> wrote:
>
> On 26/04/2023 20:56, Robert Marko wrote:
> > Add node to support the QUP5 SPI controller inside of IPQ8074.
> > Some devices use this bus in order to manage external switches.
> >
> > Signed-off-by: Robert Marko <robimarko@...il.com>
> > ---
> > arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> > index 64c2a30d9c25..4a682e3442f8 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> > @@ -774,6 +774,20 @@ blsp1_i2c5: i2c@...9000 {
> > status = "disabled";
> > };
> >
> > + blsp1_spi5: spi@...9000 {
> > + compatible = "qcom,spi-qup-v2.2.1";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x78b9000 0x600>;
>
> reg is always after compatible.
I agree usually, but here its just matching the same pattern like
other BLSP nodes.
Regards,
Robert
>
> Best regards,
> Krzysztof
>
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