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Message-ID: <958cca71-b2f2-80af-541c-d1e84b151d3c@linaro.org>
Date: Thu, 4 May 2023 08:30:54 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Jacky Huang <ychuang570808@...il.com>, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, lee@...nel.org,
mturquette@...libre.com, sboyd@...nel.org, p.zabel@...gutronix.de,
gregkh@...uxfoundation.org, jirislaby@...nel.org,
tmaimon77@...il.com, catalin.marinas@....com, will@...nel.org
Cc: devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-serial@...r.kernel.org, arnd@...db.de, schung@...oton.com,
mjchen@...oton.com, Jacky Huang <ychuang3@...oton.com>
Subject: Re: [PATCH v9 08/10] clk: nuvoton: Add clock driver for ma35d1 clock
controller
On 04/05/2023 05:37, Jacky Huang wrote:
> From: Jacky Huang <ychuang3@...oton.com>
>
> The clock controller generates clocks for the whole chip, including
> system clocks and all peripheral clocks. This driver support ma35d1
> clock gating, divider, and individual PLL configuration.
>
> There are 6 PLLs in ma35d1 SoC:
> - CA-PLL for the two Cortex-A35 CPU clock
> - SYS-PLL for system bus, which comes from the companion MCU
> and cannot be programmed by clock controller.
> - DDR-PLL for DDR
> - EPLL for GMAC and GFX, Display, and VDEC IPs.
> - VPLL for video output pixel clock
> - APLL for SDHC, I2S audio, and other IPs.
> CA-PLL has only one operation mode.
> DDR-PLL, EPLL, VPLL, and APLL are advanced PLLs which have 3
> operation modes: integer mode, fraction mode, and spread specturm mode.
>
> Signed-off-by: Jacky Huang <ychuang3@...oton.com>
> ---
> drivers/clk/Makefile | 1 +
> drivers/clk/nuvoton/Kconfig | 19 +
> drivers/clk/nuvoton/Makefile | 4 +
> drivers/clk/nuvoton/clk-ma35d1-divider.c | 140 ++++
> drivers/clk/nuvoton/clk-ma35d1-pll.c | 365 +++++++++
> drivers/clk/nuvoton/clk-ma35d1.c | 948 +++++++++++++++++++++++
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Best regards,
Krzysztof
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