linux-kernel - [PATCH V3 5/7] drm: bridge: samsung-dsim: Dynamically configure DPHY timing

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Date:   Fri,  5 May 2023 09:33:59 +0200
From:   Michael Walle <michael@...le.cc>
To:     aford173@...il.com
Cc:     Laurent.pinchart@...asonboard.com, aford@...conembedded.com,
        andrzej.hajda@...el.com, dri-devel@...ts.freedesktop.org,
        frieder.schrempf@...tron.de, jagan@...rulasolutions.com,
        jernej.skrabec@...il.com, jonas@...boo.se,
        linux-kernel@...r.kernel.org, m.szyprowski@...sung.com,
        marex@...x.de, neil.armstrong@...aro.org, rfoss@...nel.org,
        wenst@...omium.org, Michael Walle <michael@...le.cc>
Subject: [PATCH V3 5/7] drm: bridge: samsung-dsim: Dynamically configure DPHY timing

> The DPHY timings are currently hard coded. Since the input
> clock can be variable, the phy timings need to be variable
> too.  Add an additional variable to the driver data to enable
> this feature to prevent breaking boards that don't support it.
> 
> The phy_mipi_dphy_get_default_config function configures the
> DPHY timings in pico-seconds, and a small macro converts those
> timings into clock cycles based on the pixel clock rate.

This actually fixes a bug with the DSI84 bridge on our boards. The
hardcoded settings will violate the D-PHY spec timings for lower
frequencies, esp. the Ths_prepare+Ths_zero timing. Thus, the bridge
will read a wrong HS sync sequence and set it's internal SoT error
bit (and don't generate any RGB signals on the LVDS side).

Tested-by: Michael Walle <michael@...le.cc>

Thanks!
-michael