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Date: Fri, 5 May 2023 17:27:07 +0400
From: Maxim Kiselev <bigunclemax@...il.com>
To: Andre Przywara <andre.przywara@....com>
Cc: robh+dt@...nel.org,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Cristian Ciocaltea <cristian.ciocaltea@...labora.com>,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] riscv: dts: allwinner: d1: Add SPI0 controller node
Hi Andre,
> From a quick glance at the manuals, it
> looks like there are not quite the same, though: the D1/R528/T113s
> mentions a SPI_SAMP_DL register @0x28, whereas the older IP has a SPI_CCR
> register @0x24 - which is not mentioned in the newer manuals. The driver
> relies on that clock control register, so it wouldn't really work
> reliably, if that register is not there.
Thank you for pointing this out. I missed this difference.
I actually have a board with T113 SoC, and it looks like writing to
SPI_CCR@...4 does nothing.
And it doesn't affect access to connected SPI NOR flash (read\write
operations are fine).
But I completely agree with you that this difference should be handled
by the spi driver.
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