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Message-Id: <20230506010933.170939-4-aford173@gmail.com>
Date: Fri, 5 May 2023 20:09:30 -0500
From: Adam Ford <aford173@...il.com>
To: dri-devel@...ts.freedesktop.org
Cc: aford@...conembedded.com, Adam Ford <aford173@...il.com>,
Chen-Yu Tsai <wenst@...omium.org>,
Frieder Schrempf <frieder.schrempf@...tron.de>,
Andrzej Hajda <andrzej.hajda@...el.com>,
Neil Armstrong <neil.armstrong@...aro.org>,
Robert Foss <rfoss@...nel.org>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...il.com>,
David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Inki Dae <inki.dae@...sung.com>,
Jagan Teki <jagan@...rulasolutions.com>,
Marek Szyprowski <m.szyprowski@...sung.com>,
linux-kernel@...r.kernel.org
Subject: [PATCH V4 3/6] drm: bridge: samsung-dsim: Fetch pll-clock-frequency automatically
Make the pll-clock-frequency optional. If it's present, use it
to maintain backwards compatibility with existing hardware. If it
is absent, read clock rate of "sclk_mipi" to determine the rate.
Signed-off-by: Adam Ford <aford173@...il.com>
Tested-by: Chen-Yu Tsai <wenst@...omium.org>
Tested-by: Frieder Schrempf <frieder.schrempf@...tron.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@...tron.de>
---
drivers/gpu/drm/bridge/samsung-dsim.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index bf4b33d2de76..2dc02a9e37c0 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1726,12 +1726,20 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
{
struct device *dev = dsi->dev;
struct device_node *node = dev->of_node;
+ struct clk *pll_clk;
int ret;
ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
&dsi->pll_clk_rate);
- if (ret < 0)
- return ret;
+
+ /* If it doesn't exist, read it from the clock instead of failing */
+ if (ret < 0) {
+ pll_clk = devm_clk_get(dev, "sclk_mipi");
+ if (!IS_ERR(pll_clk))
+ dsi->pll_clk_rate = clk_get_rate(pll_clk);
+ else
+ return PTR_ERR(pll_clk);
+ }
ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
&dsi->burst_clk_rate);
--
2.39.2
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