[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20230507105210.1deba8c1@slackpad.lan>
Date: Sun, 7 May 2023 10:52:10 +0100
From: Andre Przywara <andre.przywara@....com>
To: Maksim Kiselev <bigunclemax@...il.com>
Cc: Icenowy Zheng <icenowy@...c.io>,
Conor Dooley <conor.dooley@...rochip.com>,
Mark Brown <broonie@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Cristian Ciocaltea <cristian.ciocaltea@...labora.com>,
Maxime Ripard <mripard@...nel.org>, linux-spi@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-sunxi@...ts.linux.dev, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v3 5/5] riscv: dts: allwinner: d1: Add SPI controllers
node
On Sun, 7 May 2023 02:26:08 +0300
Maksim Kiselev <bigunclemax@...il.com> wrote:
> Some boards form the MangoPi family (MQ\MQ-Dual\MQ-R) may have
> an optional SPI flash that connects to the SPI0 controller.
>
> This controller is the same for R329/D1/R528/T113s SoCs and
> should be supported by the sun50i-r329-spi driver.
>
> So let's add its DT nodes.
>
> Signed-off-by: Maksim Kiselev <bigunclemax@...il.com>
> Acked-by: Conor Dooley <conor.dooley@...rochip.com>
Looks alright, thanks for the changes:
Reviewed-by: Andre Przywara <andre.przywara@....com>
Cheers,
Andre
> ---
> .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 37 +++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> index 922e8e0e2c09..1bb1e5cae602 100644
> --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> @@ -108,6 +108,12 @@ rmii_pe_pins: rmii-pe-pins {
> function = "emac";
> };
>
> + /omit-if-no-ref/
> + spi0_pins: spi0-pins {
> + pins = "PC2", "PC3", "PC4", "PC5";
> + function = "spi0";
> + };
> +
> /omit-if-no-ref/
> uart1_pg6_pins: uart1-pg6-pins {
> pins = "PG6", "PG7";
> @@ -447,6 +453,37 @@ mmc2: mmc@...2000 {
> #size-cells = <0>;
> };
>
> + spi0: spi@...5000 {
> + compatible = "allwinner,sun20i-d1-spi",
> + "allwinner,sun50i-r329-spi";
> + reg = <0x04025000 0x1000>;
> + interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 22>, <&dma 22>;
> + dma-names = "rx", "tx";
> + resets = <&ccu RST_BUS_SPI0>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi1: spi@...6000 {
> + compatible = "allwinner,sun20i-d1-spi-dbi",
> + "allwinner,sun50i-r329-spi-dbi",
> + "allwinner,sun50i-r329-spi";
> + reg = <0x04026000 0x1000>;
> + interrupts = <SOC_PERIPHERAL_IRQ(16) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 23>, <&dma 23>;
> + dma-names = "rx", "tx";
> + resets = <&ccu RST_BUS_SPI1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> usb_otg: usb@...0000 {
> compatible = "allwinner,sun20i-d1-musb",
> "allwinner,sun8i-a33-musb";
Powered by blists - more mailing lists