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Message-ID: <20230508-shining-slug-ac097b6e84ae@wendy>
Date:   Mon, 8 May 2023 08:07:37 +0100
From:   Conor Dooley <conor.dooley@...rochip.com>
To:     Guo Ren <guoren@...nel.org>
CC:     Jisheng Zhang <jszhang@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-riscv@...ts.infradead.org>
Subject: Re: [PATCH 1/5] irqchip/sifive-plic: Support T-HEAD's C910 PLIC

On Mon, May 08, 2023 at 02:52:29PM +0800, Guo Ren wrote:

> Another question, Could we change the name of Sifive to RISC-V when
> "cat /proc/interrupts" ?

Previously NAKed by Marc as it is ABI:
https://lore.kernel.org/all/20511a05f39408c8ffbcc98923c4abd2@kernel.org

Cheers,
Conor.

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