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Message-ID: <87jzxjp5tp.fsf@oltmanns.dev>
Date: Mon, 08 May 2023 10:47:41 +0200
From: Frank Oltmanns <frank@...manns.dev>
To: Roman Beranek <me@...y.cz>
Cc: Maxime Ripard <mripard@...nel.org>,
David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>, Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Icenowy Zheng <icenowy@...c.io>, Ondrej Jirman <megi@....cz>,
devicetree@...r.kernel.org, dri-devel@...ts.freedesktop.org,
linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 0/4] drm: sun4i: set proper TCON0 DCLK rate in DSI mode
Hi Roman,
On 2023-05-05 at 07:21:06 +0200, Roman Beranek <me@...y.cz> wrote:
> According to Allwinner's BSP code, in DSI mode, TCON0 clock needs to be
> running at what's effectively the per-lane datarate of the DSI link.
> Given that the TCON DCLK divider is fixed to 4 (SUN6I_DSI_TCON_DIV),
> DCLK can't be set equal to the dotclock. Therefore labeling TCON DCLK
> as sun4i_dotclock or tcon-pixel-clock shall be avoided.
>
> With bpp bits per pixel transmitted over n DSI lanes, the target DCLK
> rate for a given pixel clock is obtained as follows:
>
> DCLK rate = 1/4 * bpp / n * pixel clock
>
> Effect of this change can be observed through the rate of Vblank IRQs
> which should now match refresh rate implied by set display mode. It
> was verified to do so on a A64 board with a 2-lane and a 4-lane panel.
>
> v2:
> 1. prevent reparent of tcon0 to pll-video0-2x
> 2. include pll-video0 in setting TCON0 DCLK rate
> 3. tested the whole thing also on a PinePhone
>
> v3:
> 1. accept that pll-video0 can't be included in setting TCON0 DCLK rate
> 2. reset pll-video0 to its default rate in case u-boot changed it
>
> v4:
> 1. keep pll-video0 as is
> 2. assign parent to TCON0 mux in sun50i_a64_ccu_probe (not in DT)
>
> Roman Beranek (4):
> clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux
> ARM: dts: sunxi: rename tcon's clock output
> drm: sun4i: rename sun4i_dotclock to sun4i_tcon_dclk
> drm: sun4i: calculate proper DCLK rate for DSI
>
> arch/arm/boot/dts/sun5i.dtsi | 2 +-
> arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
> arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
> arch/arm/boot/dts/sun8i-v3s.dtsi | 2 +-
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 +-
> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 14 +++++-
> drivers/gpu/drm/sun4i/Makefile | 2 +-
> drivers/gpu/drm/sun4i/sun4i_tcon.c | 46 +++++++++++--------
> .../{sun4i_dotclock.c => sun4i_tcon_dclk.c} | 2 +-
> .../{sun4i_dotclock.h => sun4i_tcon_dclk.h} | 0
> 10 files changed, 46 insertions(+), 28 deletions(-)
> rename drivers/gpu/drm/sun4i/{sun4i_dotclock.c => sun4i_tcon_dclk.c} (99%)
> rename drivers/gpu/drm/sun4i/{sun4i_dotclock.h => sun4i_tcon_dclk.h} (100%)
>
>
> base-commit: 8a91b29f1f50ce7742cdbe5cf11d17f128511f3f
I tested this on my pinephone on drm-next, using additional patches for
the pinephone's panel. [1] [2] [3]
I played back a 60 fps video (10 seconds) and recorded the panel's
output with a 240 fps camera. I noticed only 2 dropped frames, that I
account to the imperfect data rate of 107.8MHz instead of 108 MHz due to
pll-video0's rate being 294MHz instead of the 297 MHz for reasons I
described in the thread on your v2 of this patch [4]).
Tested-by: Frank Oltmanns <frank@...manns.dev>
Thanks,
Frank
[1]: https://lore.kernel.org/all/20230213123238.76889-2-frank@oltmanns.dev/
[2]: https://lore.kernel.org/all/20230211171748.36692-2-frank@oltmanns.dev/
[3]: https://github.com/megous/linux/commit/e83ffbfe930562257abef1eed4abb8e2251b795a
[4]: https://lore.kernel.org/all/87cz3uzpx1.fsf@oltmanns.dev/
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