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Message-ID: <20230508-margarita-fondling-c9b970ad73a9@spud>
Date: Mon, 8 May 2023 20:24:53 +0100
From: Conor Dooley <conor@...nel.org>
To: Xingyu Wu <xingyu.wu@...rfivetech.com>
Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Emil Renner Berthing <kernel@...il.dk>,
Rob Herring <robh+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Hal Feng <hal.feng@...rfivetech.com>,
William Qiu <william.qiu@...rfivetech.com>,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH v3 5/7] dt-bindings: soc: starfive: Add StarFive syscon
module
On Mon, Apr 24, 2023 at 06:15:47PM +0100, Conor Dooley wrote:
> On Fri, Apr 14, 2023 at 10:41:55AM +0800, Xingyu Wu wrote:
> > From: William Qiu <william.qiu@...rfivetech.com>
> >
> > Add documentation to describe StarFive System Controller Registers.
> >
> > Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
> > ---
> > .../soc/starfive/starfive,jh7110-syscon.yaml | 58 +++++++++++++++++++
> > MAINTAINERS | 6 ++
> > 2 files changed, 64 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> > new file mode 100644
> > index 000000000000..de086e74a229
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> > @@ -0,0 +1,58 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: StarFive JH7110 SoC system controller
> > +
> > +maintainers:
> > + - William Qiu <william.qiu@...rfivetech.com>
> > +
> > +description: |
> > + The StarFive JH7110 SoC system controller provides register information such
> > + as offset, mask and shift to configure related modules such as MMC and PCIe.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - enum:
> > + - starfive,jh7110-aon-syscon
> > + - starfive,jh7110-sys-syscon
> > + - const: syscon
> > + - const: simple-mfd
> > + - items:
> > + - const: starfive,jh7110-stg-syscon
> > + - const: syscon
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clock-controller:
> > + $ref: /schemas/clock/starfive,jh7110-pll.yaml#
> > + type: object
> > +
> > + power-controller:
> > + $ref: /schemas/power/starfive,jh7110-pmu.yaml#
> > + type: object
>
> My plan was to grab this patch after the merge window, but there's been
> some back and forth [1] about what exactly should be a power-controller
> here. Given the merge window is open & I know Emil wants to look at the
> various clock bits for the JH7110, I don't think there's a pressing need
> for you to do anything here, but figured I'd at least mention how things
> are going on this thread too.
To follow up on this, it transpired in that thread that this node, not a
child node, should be the power controller.
Up to you StarFive folk how you wish to resend, but I am fine with it
being in this series, I shall just not pick up the soc driver patches
until the resent binding is applied by Stephen.
Thanks,
Conor.
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