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Message-ID: <2d60886f-a731-ee29-dd2e-1a1438bd7d03@quicinc.com>
Date: Tue, 9 May 2023 14:39:36 +0530
From: Taniya Das <quic_tdas@...cinc.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Andy Gross <agross@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Richard Cochran <richardcochran@...il.com>,
Michael Turquette <mturquette@...libre.com>
CC: <quic_skakitap@...cinc.com>,
Imran Shaik <quic_imrashai@...cinc.com>,
<linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<quic_rohiagar@...cinc.com>, <netdev@...r.kernel.org>
Subject: Re: [PATCH 2/4] dt-bindings: clock: Add GCC bindings support for
SDX75
Thanks for the review.
On 4/19/2023 11:41 PM, Krzysztof Kozlowski wrote:
> On 19/04/2023 15:30, Taniya Das wrote:
>> From: Imran Shaik <quic_imrashai@...cinc.com>
>>
>
> Thank you for your patch. There is something to discuss/improve.
>
>> Add support for GCC bindings and update documentation for
>> clock rpmh driver for SDX75.
>
> Subject: drop second/last, redundant "bindings support for". The
> "dt-bindings" prefix is already stating that these are bindings.
> But missing vendor name (Qualcomm). Both in subject and commit msg.
>
>
All the below comments will be taken care in the next patchset.
>
>>
>> Signed-off-by: Imran Shaik <quic_imrashai@...cinc.com>
>> Signed-off-by: Taniya Das <quic_tdas@...cinc.com>
>> ---
>> .../bindings/clock/qcom,gcc-sdx75.yaml | 69 +++++++
>> .../bindings/clock/qcom,rpmhcc.yaml | 1 +
>> include/dt-bindings/clock/qcom,gcc-sdx75.h | 193 ++++++++++++++++++
>> 3 files changed, 263 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sdx75.yaml
>> create mode 100644 include/dt-bindings/clock/qcom,gcc-sdx75.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx75.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx75.yaml
>> new file mode 100644
>> index 000000000000..6489d857d5c4
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx75.yaml
>
> All new devices come as SoC-IP, so qcom,sdx75-gcc
>
>> @@ -0,0 +1,69 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx75.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Global Clock & Reset Controller on SDX75
>> +
>> +maintainers:
>> + - Imran Shaik <quic_imrashai@...cinc.com>
>> + - Taniya Das <quic_tdas@...cinc.com>
>> +
>> +description: |
>> + Qualcomm global clock control module provides the clocks, resets and power
>> + domains on SDX75
>> +
>> + See also:: include/dt-bindings/clock/qcom,gcc-sdx75.h
>
> Also hee
>
>> +
>> +properties:
>> + compatible:
>> + const: qcom,gcc-sdx75
>
> Also here
>
>> +
>> + clocks:
>> + items:
>> + - description: Board XO source
>> + - description: PCIE20 phy aux clock source
>> + - description: PCIE_1 Pipe clock source
>> + - description: PCIE_2 Pipe clock source
>> + - description: PCIE Pipe clock source
>> + - description: Sleep clock source
>> + - description: USB3 phy wrapper pipe clock source
>> +
>> + clock-names:
>> + items:
>> + - const: bi_tcxo
>> + - const: pcie20_phy_aux_clk
>> + - const: pcie_1_pipe_clk
>> + - const: pcie_2_pipe_clk
>> + - const: pcie_pipe_clk
>> + - const: sleep_clk
>> + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
>
> Drop clock names entirely.
>
>> +
>> +required:
>> + - compatible
>> + - clocks
>> + - clock-names
>> +
>> +allOf:
>> + - $ref: qcom,gcc.yaml#
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,rpmh.h>
>> + clock-controller@...00 {
>> + compatible = "qcom,gcc-sdx75";
>> + reg = <0x80000 0x1f7400>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>,
>> + <&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&sleep_clk>,
>> + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
>> + clock-names = "bi_tcxo", "pcie20_phy_aux_clk", "pcie_1_pipe_clk",
>> + "pcie_2_pipe_clk", "pcie_pipe_clk", "sleep_clk",
>> + "usb3_phy_wrapper_gcc_usb30_pipe_clk";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +...
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
>> index d5a250b7c2af..267cf8c26823 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
>> @@ -27,6 +27,7 @@ properties:
>> - qcom,sdm845-rpmh-clk
>> - qcom,sdx55-rpmh-clk
>> - qcom,sdx65-rpmh-clk
>> + - qcom,sdx75-rpmh-clk
>
> Separate patch.
>
>
>> - qcom,sm6350-rpmh-clk
>> - qcom,sm8150-rpmh-clk
>> - qcom,sm8250-rpmh-clk
>> diff --git a/include/dt-bindings/clock/qcom,gcc-sdx75.h b/include/dt-bindings/clock/qcom,gcc-sdx75.h
>> new file mode 100644
>> index 000000000000..a470e8c4fd41
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/qcom,gcc-sdx75.h
>
> qcom,sdx75-gcc
>
>> @@ -0,0 +1,193 @@
>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>> +/*
>> + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H
>> +#define _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H
>> +
>> +/* GCC clocks */
>
>
> Best regards,
> Krzysztof
>
--
Thanks & Regards,
Taniya Das.
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