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Date: Tue, 9 May 2023 22:32:53 +0530
From: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
To: Sricharan Ramabadhran <quic_srichara@...cinc.com>,
<agross@...nel.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <jassisinghbrar@...il.com>,
<mathieu.poirier@...aro.org>, <mturquette@...libre.com>,
<sboyd@...nel.org>, <quic_gurus@...cinc.com>,
<loic.poulain@...aro.org>, <quic_eberman@...cinc.com>,
<robimarko@...il.com>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-remoteproc@...r.kernel.org>, <linux-clk@...r.kernel.org>
CC: <quic_gokulsri@...cinc.com>, <quic_sjaganat@...cinc.com>,
<quic_kathirav@...cinc.com>, <quic_arajkuma@...cinc.com>,
<quic_anusha@...cinc.com>, <quic_poovendh@...cinc.com>
Subject: Re: [PATCH 06/11] clk: qcom: IPQ9574: Add q6/wcss clocks
On 3/7/2023 12:58 PM, Sricharan Ramabadhran wrote:
>
>
> On 3/7/2023 10:11 AM, Manikanta Mylavarapu wrote:
>> Some of the clocks required for q6/wcss bring up
>> are missing. So this patch adds clocks.
>>
>> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
>> ---
>> drivers/clk/qcom/gcc-ipq9574.c | 119 +++++++++++++++++++++++++++++++++
>> 1 file changed, 119 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/gcc-ipq9574.c
>> b/drivers/clk/qcom/gcc-ipq9574.c
>> index 1bf33d582dc2..355f2e12d9c6 100644
>> --- a/drivers/clk/qcom/gcc-ipq9574.c
>> +++ b/drivers/clk/qcom/gcc-ipq9574.c
>> @@ -2697,6 +2697,22 @@ static struct clk_branch gcc_wcss_acmt_clk = {
>> },
>> };
>> +static struct clk_branch gcc_wcss_ahb_s_clk = {
>> + .halt_reg = 0x25060,
>> + .clkr = {
>> + .enable_reg = 0x25060,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_wcss_ahb_s_clk",
>> + .parent_hws = (const struct clk_hw *[]){
>> + &wcss_ahb_clk_src.clkr.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
>> .halt_reg = 0x2e030,
>> .clkr = {
>> @@ -2734,6 +2750,22 @@ static struct clk_rcg2 wcss_axi_m_clk_src = {
>> },
>> };
>> +static struct clk_branch gcc_wcss_axi_m_clk = {
>> + .halt_reg = 0x25064,
>> + .clkr = {
>> + .enable_reg = 0x25064,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_wcss_axi_m_clk",
>> + .parent_hws = (const struct clk_hw *[]){
>> + &wcss_axi_m_clk_src.clkr.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> static struct clk_branch gcc_anoc_wcss_axi_m_clk = {
>> .halt_reg = 0x2e0a8,
>> .clkr = {
>> @@ -2803,6 +2835,22 @@ static struct clk_branch
>> gcc_wcss_dbg_ifc_atb_clk = {
>> },
>> };
>> +static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {
>> + .halt_reg = 0x2504C,
>> + .clkr = {
>> + .enable_reg = 0x2504C,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_wcss_dbg_ifc_atb_bdg_clk",
>> + .parent_hws = (const struct clk_hw *[]){
>> + &qdss_at_clk_src.clkr.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> static struct clk_branch gcc_nssnoc_atb_clk = {
>> .halt_reg = 0x17014,
>> .clkr = {
>> @@ -3073,6 +3121,22 @@ static struct clk_branch
>> gcc_wcss_dbg_ifc_nts_clk = {
>> },
>> };
>> +static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {
>> + .halt_reg = 0x25050,
>> + .clkr = {
>> + .enable_reg = 0x25050,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_wcss_dbg_ifc_nts_bdg_clk",
>> + .parent_hws = (const struct clk_hw *[]){
>> + &qdss_tsctr_div2_clk_src.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> static struct clk_branch gcc_qdss_tsctr_div2_clk = {
>> .halt_reg = 0x2d044,
>> .clkr = {
>> @@ -3315,6 +3379,38 @@ static struct clk_branch
>> gcc_wcss_dbg_ifc_dapbus_clk = {
>> },
>> };
>> +static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {
>> + .halt_reg = 0x25048,
>> + .clkr = {
>> + .enable_reg = 0x25048,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_wcss_dbg_ifc_apb_bdg_clk",
>> + .parent_hws = (const struct clk_hw *[]){
>> + &qdss_dap_sync_clk_src.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = {
>> + .halt_reg = 0x25054,
>> + .clkr = {
>> + .enable_reg = 0x25054,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk",
>> + .parent_hws = (const struct clk_hw *[]){
>> + &qdss_dap_sync_clk_src.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> static struct clk_branch gcc_qdss_dap_clk = {
>> .halt_reg = 0x2d058,
>> .clkr = {
>> @@ -3513,6 +3609,22 @@ static struct clk_rcg2 q6_axim2_clk_src = {
>> },
>> };
>> +static struct clk_branch gcc_q6_axim2_clk = {
>> + .halt_reg = 0x25010,
>> + .clkr = {
>> + .enable_reg = 0x25010,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_q6_axim2_clk",
>> + .parent_hws = (const struct clk_hw *[]){
>> + &q6_axim2_clk_src.clkr.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>
> These clocks does not seem to be used in the driver, where are they used ?
>
> Regards,
> Sricharan
Clocks in multipd architecture will be handled by QDSP6 firmware.
So i am going to remove clock handling and drop this patch.
Thanks & Regards,
Manikanta.
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