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Message-Id: <20230510204456.57202-1-frank.li@vivo.com>
Date: Thu, 11 May 2023 04:44:52 +0800
From: Yangtao Li <frank.li@...o.com>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
Cc: Jisheng Zhang <jszhang@...nel.org>, Icenowy Zheng <uwu@...nowy.me>,
Wei Fu <wefu@...hat.com>, Yangtao Li <frank.li@...o.com>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH v2 1/5] riscv: Add the T-HEAD SoC family Kconfig option
From: Jisheng Zhang <jszhang@...nel.org>
The first SoC in the T-HEAD series is light(a.k.a th1520), containing
quad T-HEAD C910 cores.
Cc: Icenowy Zheng <uwu@...nowy.me>
Cc: Wei Fu <wefu@...hat.com>
Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
Signed-off-by: Yangtao Li <frank.li@...o.com>
---
arch/riscv/Kconfig.socs | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 1cf69f958f10..ce10a38dff37 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -41,6 +41,12 @@ config ARCH_SUNXI
This enables support for Allwinner sun20i platform hardware,
including boards based on the D1 and D1s SoCs.
+config ARCH_THEAD
+ bool "T-HEAD RISC-V SoCs"
+ select ERRATA_THEAD
+ help
+ This enables support for the RISC-V based T-HEAD SoCs.
+
config ARCH_VIRT
def_bool SOC_VIRT
--
2.34.1
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