linux-kernel - Re: [PATCH v3 5/5] arm64: dts: meson: a1: support USB controller in OTG mode

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Date:   Thu, 11 May 2023 23:24:54 +0300
From:   Dmitry Rokosov <ddrokosov@...rdevices.ru>
To:     <neil.armstrong@...aro.org>
CC:     <gregkh@...uxfoundation.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <khilman@...libre.com>,
        <jbrunet@...libre.com>, <martin.blumenstingl@...glemail.com>,
        <mturquette@...libre.com>, <vkoul@...nel.org>, <kishon@...nel.org>,
        <hminas@...opsys.com>, <Thinh.Nguyen@...opsys.com>,
        <yue.wang@...ogic.com>, <hanjie.lin@...ogic.com>,
        <kernel@...rdevices.ru>, <rockosov@...il.com>,
        <linux-usb@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-amlogic@...ts.infradead.org>,
        <linux-phy@...ts.infradead.org>
Subject: Re: [PATCH v3 5/5] arm64: dts: meson: a1: support USB controller in
 OTG mode

Hello Neil,

I apologize for the delayed response, as I did not have access to my laptop
for a few days.

On Tue, May 09, 2023 at 09:44:33AM +0200, neil.armstrong@...aro.org wrote:
> Hi,
> 
> On 26/04/2023 12:29, Dmitry Rokosov wrote:
> > Amlogic A1 SoC family has USB2.0 controller based on dwc2 and dwc3
> > heads. It supports otg/host/peripheral modes.
> > 
> > Signed-off-by: Yue Wang <yue.wang@...ogic.com>
> > Signed-off-by: Hanjie Lin <hanjie.lin@...ogic.com>
> > Signed-off-by: Dmitry Rokosov <ddrokosov@...rdevices.ru>
> > ---
> >   arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 59 +++++++++++++++++++++++
> >   1 file changed, 59 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > index ae7d39cff07a..5588ee602161 100644
> > --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > @@ -8,6 +8,8 @@
> >   #include <dt-bindings/gpio/meson-a1-gpio.h>
> >   #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
> >   #include <dt-bindings/clock/amlogic,a1-clkc.h>
> > +#include <dt-bindings/power/meson-a1-power.h>
> > +#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
> >   / {
> >   	compatible = "amlogic,a1";
> > @@ -169,6 +171,17 @@ gpio_intc: interrupt-controller@...0 {
> >   				amlogic,channel-interrupts =
> >   					<49 50 51 52 53 54 55 56>;
> >   			};
> > +
> > +			usb2_phy1: phy@...0 {
> > +				compatible = "amlogic,a1-usb2-phy";
> > +				clocks = <&clkc CLKID_USB_PHY_IN>;
> > +				clock-names = "xtal";
> > +				reg = <0x0 0x4000 0x0 0x60>;
> > +				resets = <&reset RESET_USBPHY>;
> > +				reset-names = "phy";
> > +				#phy-cells = <0>;
> > +				power-domains = <&pwrc PWRC_USB_ID>;
> > +			};
> >   		};
> >   		gic: interrupt-controller@...01000 {
> > @@ -192,6 +205,52 @@ spifc: spi@...00400 {
> >   			#size-cells = <0>;
> >   			status = "disabled";
> >   		};
> > +
> > +		usb: usb@...04400 {
> > +			status = "disabled";
> > +			compatible = "amlogic,meson-a1-usb-ctrl";
> > +			reg = <0x0 0xfe004400 0x0 0xa0>;
> > +			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> > +			#address-cells = <2>;
> > +			#size-cells = <2>;
> > +			ranges;
> > +
> > +			clocks = <&clkc CLKID_USB_CTRL>,
> > +				 <&clkc CLKID_USB_BUS>,
> > +				 <&clkc CLKID_USB_CTRL_IN>;
> > +			clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
> > +			resets = <&reset RESET_USBCTRL>;
> > +			reset-name = "usb_ctrl";
> > +
> > +			dr_mode = "otg";
> > +
> > +			phys = <&usb2_phy1>;
> > +			phy-names = "usb2-phy1";
> > +
> > +			dwc2: usb@...00000 {
> > +				compatible = "amlogic,meson-a1-usb", "snps,dwc2";
> > +				reg = <0x0 0xff500000 0x0 0x40000>;
> > +				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> > +				phys = <&usb2_phy1>;
> > +				phy-names = "usb2-phy";
> > +				clocks = <&clkc CLKID_USB_PHY>;
> > +				clock-names = "otg";
> > +				dr_mode = "peripheral";
> > +				g-rx-fifo-size = <192>;
> > +				g-np-tx-fifo-size = <128>;
> > +				g-tx-fifo-size = <128 128 16 16 16>;
> > +			};
> > +
> > +			dwc3: usb@...00000 {
> > +				compatible = "snps,dwc3";
> > +				reg = <0x0 0xff400000 0x0 0x100000>;
> > +				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> > +				dr_mode = "host";
> > +				snps,dis_u2_susphy_quirk;
> > +				snps,quirk-frame-length-adjustment = <0x20>;
> > +				snps,parkmode-disable-ss-quirk;
> > +			};
> > +		};
> >   	};
> >   	timer {
> 
> This patcj is fine, but depends on clock bindings & dt, so now Vinod took the PHY
> patch, please resend this wiyhout patches 1 & 5, then resend the DT patch later when
> the clock bindings is merged.
> 
> Thanks,
> Neil

Sure, not a problem. I will resend the 3 patchsets in different series.

-- 
Thank you,
Dmitry