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Message-ID: <20230511150539.6.Ia0b6ebbaa351e3cd67e201355b9ae67783c7d718@changeid>
Date: Thu, 11 May 2023 15:05:40 -0700
From: Douglas Anderson <dianders@...omium.org>
To: Marc Zyngier <maz@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Matthias Brugger <matthias.bgg@...il.com>
Cc: devicetree@...r.kernel.org, linux-mediatek@...ts.infradead.org,
wenst@...omium.org, Eddie Huang <eddie.huang@...iatek.com>,
Allen-KH Cheng <allen-kh.cheng@...iatek.com>,
Ben Ho <Ben.Ho@...iatek.com>, Weiyi Lu <weiyi.lu@...iatek.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
linux-arm-kernel@...ts.infradead.org,
Tinghan Shen <tinghan.shen@...iatek.com>, jwerner@...omium.org,
Hsin-Hsiung Wang <hsin-hsiung.wang@...iatek.com>,
yidilin@...omium.org, Seiya Wang <seiya.wang@...iatek.com>,
Douglas Anderson <dianders@...omium.org>,
Conor Dooley <conor+dt@...nel.org>,
linux-kernel@...r.kernel.org
Subject: [PATCH 6/6] arm64: dts: mediatek: mt8195: Add mediatek,gicr-save-quirk
Firmware shipped on mt8195 Chromebooks is affected by the GICR
save/restore issue as described by the patch ("dt-bindings:
interrupt-controller: arm,gic-v3: Add quirk for Mediatek SoCs w/
broken FW"). Add the quirk property.
Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board")
Signed-off-by: Douglas Anderson <dianders@...omium.org>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index a44aae4ab953..6df9ad8f658f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -463,6 +463,7 @@ gic: interrupt-controller@...0000 {
reg = <0 0x0c000000 0 0x40000>,
<0 0x0c040000 0 0x200000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gicr-save-quirk;
ppi-partitions {
ppi_cluster0: interrupt-partition-0 {
--
2.40.1.606.ga4b1b128d6-goog
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