Message-ID: <MW5PR12MB55986A4865DB56F7F024EA7687749@MW5PR12MB5598.namprd12.prod.outlook.com>
Date:   Thu, 11 May 2023 11:32:05 +0000
From:   "Gaddam, Sarath Babu Naidu" <sarath.babu.naidu.gaddam@....com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "edumazet@...gle.com" <edumazet@...gle.com>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "pabeni@...hat.com" <pabeni@...hat.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>
CC:     "linux@...linux.org.uk" <linux@...linux.org.uk>,
        "Simek, Michal" <michal.simek@....com>,
        "Pandey, Radhey Shyam" <radhey.shyam.pandey@....com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "Sarangi, Anirudha" <anirudha.sarangi@....com>,
        "Katakam, Harini" <harini.katakam@....com>,
        "git (AMD-Xilinx)" <git@....com>
Subject: RE: [PATCH net-next V3 1/3] dt-bindings: net: xilinx_axienet:
 Introduce dmaengine binding support



> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Sent: Wednesday, May 10, 2023 3:39 PM
> To: Gaddam, Sarath Babu Naidu
> <sarath.babu.naidu.gaddam@....com>; davem@...emloft.net;
> edumazet@...gle.com; kuba@...nel.org; pabeni@...hat.com;
> robh+dt@...nel.org; krzysztof.kozlowski+dt@...aro.org
> Cc: linux@...linux.org.uk; Simek, Michal <michal.simek@....com>;
> Pandey, Radhey Shyam <radhey.shyam.pandey@....com>;
> netdev@...r.kernel.org; devicetree@...r.kernel.org; linux-arm-
> kernel@...ts.infradead.org; linux-kernel@...r.kernel.org; Sarangi,
> Anirudha <anirudha.sarangi@....com>; Katakam, Harini
> <harini.katakam@....com>; git (AMD-Xilinx) <git@....com>
> Subject: Re: [PATCH net-next V3 1/3] dt-bindings: net: xilinx_axienet:
> Introduce dmaengine binding support
> 
> On 10/05/2023 10:50, Sarath Babu Naidu Gaddam wrote:
> > From: Radhey Shyam Pandey <radhey.shyam.pandey@...inx.com>
> >
> > The axiethernet driver will use dmaengine framework to communicate
> > with dma controller IP instead of built-in dma programming sequence.
> 
> Subject: drop second/last, redundant "bindings". The "dt-bindings"
> prefix is already stating that these are bindings.
> 
> Actually also drop "dmaenging" as it is Linuxism. Focus on hardware, e.g.
> "Add DMA support".
> 
> >
> > To request dma transmit and receive channels the axiethernet driver
> > uses generic dmas, dma-names properties.
> >
> > Also to support the backward compatibility, use "dmas" property to
> > identify as it should use dmaengine framework or legacy
> > driver(built-in dma programming).
> >
> > At this point it is recommended to use dmaengine framework but it's
> > optional. Once the solution is stable will make dmas as required
> > properties.
> >
> > Signed-off-by: Radhey Shyam Pandey
> <radhey.shyam.pandey@...inx.com>
> > Signed-off-by: Sarath Babu Naidu Gaddam
> > <sarath.babu.naidu.gaddam@....com>
> > ---
> > These changes are on top of below txt to yaml conversion discussion
> > https://lore.kernel.org/all/20230308061223.1358637-1-
> sarath.babu.naidu
> > .gaddam@....com/#Z2e.:20230308061223.1358637-1-
> sarath.babu.naidu.gadda
> > m::40amd.com:1bindings:net:xlnx::2caxi-ethernet.yaml
> >
> > Changes in V3:
> > 1) Reverted reg and interrupts property to  support backward
> compatibility.
> > 2) Moved dmas and dma-names properties from Required properties.
> >
> > Changes in V2:
> > - None.
> > ---
> >  .../devicetree/bindings/net/xlnx,axi-ethernet.yaml   | 12
> ++++++++++++
> >  1 file changed, 12 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
> > b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
> > index 80843c177029..9dfa1976e260 100644
> > --- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
> > +++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
> > @@ -122,6 +122,16 @@ properties:
> >        modes, where "pcs-handle" should be used to point to the PCS/PMA
> PHY,
> >        and "phy-handle" should point to an external PHY if exists.
> >
> > +  dmas:
> > +    items:
> > +      - description: TX DMA Channel phandle and DMA request line
> number
> > +      - description: RX DMA Channel phandle and DMA request line
> > + number
> > +
> > +  dma-names:
> > +    items:
> > +      - const: tx_chan0
> 
> tx
> 
> > +      - const: rx_chan0
> 
> rx

We want to support more channels in the future, currently we support
AXI DMA which has only one tx and rx channel. In future we want to 
extend support for multichannel DMA (MCDMA) which has 16 TX and
16 RX channels. To uniquely identify each channel, we are using chan
suffix. Depending on the usecase AXI ethernet driver can request any
combination of multichannel DMA  channels.

dma-names = tx_chan0, tx_chan1, rx_chan0, rx_chan1;

will update the commit message with same.
 
> Why doing these differently than all other devices?

To make the axi ethernet driver generic to be hooked to any complaint
dma IP i.e AXIDMA, AXIMCDMA without any modification.The inspiration
behind this dmaengine adoption is to reuse the in-kernel xilinx dma engine
driver and remove redundant dma programming sequence from the
ethernet driver.

Above information is explained in the cover letter
https://lore.kernel.org/all/20230510085031.1116327-1-sarath.babu.naidu.gaddam@amd.com/

Thanks,
Sarath

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