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Message-ID: <CAF6AEGuX721j41jCco1B6F_TW3EO3_W6+JDmh3S7Dfd62iAv7A@mail.gmail.com>
Date: Thu, 11 May 2023 07:57:51 -0700
From: Rob Clark <robdclark@...il.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: dri-devel@...ts.freedesktop.org, iommu@...ts.linux-foundation.org,
freedreno@...ts.freedesktop.org, linux-arm-msm@...r.kernel.org,
Rob Clark <robdclark@...omium.org>,
Lepton Wu <lepton@...omium.org>, Will Deacon <will@...nel.org>,
Robin Murphy <robin.murphy@....com>,
Joerg Roedel <joro@...tes.org>,
Sai Prakash Ranjan <quic_saipraka@...cinc.com>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Bjorn Andersson <quic_bjorande@...cinc.com>,
Elliot Berman <quic_eberman@...cinc.com>,
Marijn Suijten <marijn.suijten@...ainline.org>,
Emma Anholt <emma@...olt.net>,
"moderated list:ARM SMMU DRIVERS"
<linux-arm-kernel@...ts.infradead.org>,
"open list:IOMMU SUBSYSTEM" <iommu@...ts.linux.dev>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] iommu/arm-smmu-qcom: Fix missing adreno_smmu's
On Thu, May 11, 2023 at 7:51 AM Dmitry Baryshkov
<dmitry.baryshkov@...aro.org> wrote:
>
> On Tue, 9 May 2023 at 19:37, Rob Clark <robdclark@...il.com> wrote:
> >
> > From: Rob Clark <robdclark@...omium.org>
> >
> > When the special handling of qcom,adreno-smmu was moved into
> > qcom_smmu_create(), it was overlooked that we didn't have all the
> > required entries in qcom_smmu_impl_of_match. So we stopped getting
> > adreno_smmu_priv on sc7180, breaking per-process pgtables.
> >
> > Fixes: 30b912a03d91 ("iommu/arm-smmu-qcom: Move the qcom,adreno-smmu check into qcom_smmu_create")
> > Suggested-by: Lepton Wu <lepton@...omium.org>
> > Signed-off-by: Rob Clark <robdclark@...omium.org>
> > ---
> > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> > index d1b296b95c86..760d9c43dbd2 100644
> > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> > @@ -496,20 +496,21 @@ static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
> > /*
> > * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
> > * special handling and can not be covered by the qcom,smmu-500 entry.
> > */
> > static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
> > { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
> > { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
> > { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
> > { .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data },
> > { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
> > + { .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data },
> > { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
> > { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
> > { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
> > { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
> > { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },
> > { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
> > { .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data},
> > { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
> > { .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data },
> > { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
> > @@ -540,12 +541,14 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
> > /* Match platform for ACPI boot */
> > if (acpi_match_platform_list(qcom_acpi_platlist) >= 0)
> > return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data);
> > }
> > #endif
> >
> > match = of_match_node(qcom_smmu_impl_of_match, np);
> > if (match)
> > return qcom_smmu_create(smmu, match->data);
> >
> > + WARN_ON(of_device_is_compatible(np, "qcom,adreno-smmu"));
>
> Could you please add a comment here, noting the reason? Or maybe we
> should change that to:
> if (WARN_ON(...))
> return ERR_PTR(-EINVAL);
I'll add a comment. Not having an iommu is even worse, so returning
an error isn't a good idea. I just wanted to leave some breadcrumbs
so people can see where the problem actually is if per-process
pgtables break again.
BR,
-R
>
> > +
> > return smmu;
> > }
> > --
> > 2.40.1
> >
>
>
> --
> With best wishes
> Dmitry
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