From 25986bfb60d350a3fc6c865fc62255dae3e0036e Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 12 May 2023 21:20:03 +0200 Subject: [PATCH] drm: bridge: samsung-dsim: use HS clock to calculate PHY timings The current PHY timing calculation assumes that the HS clock is scaled with the mode pixelclock, which isn't always the case. Use the HS clock directly to calculate the timing parameters. Also it doesn't make much sense to scale the timings by dividing by the mode pixel clock, as the PHY never gets to see this clock. Use the byteclock instead, which seems much more likely to be the correct source driving those counters. Signed-off-by: Lucas Stach --- drivers/gpu/drm/bridge/samsung-dsim.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index cacad130cfb05..ab34adb79c158 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -713,19 +713,18 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi) const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; const unsigned int *reg_values = driver_data->reg_values; u32 reg; - struct drm_display_mode *m = &dsi->mode; - int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); struct phy_configure_opts_mipi_dphy cfg; int clk_prepare, lpx, clk_zero, clk_post, clk_trail; int hs_exit, hs_prepare, hs_zero, hs_trail; - unsigned long long clock_in_hz = m->clock * 1000; + unsigned long long byte_clock = dsi->hs_clock / 8; if (driver_data->has_freqband) return; /* The dynamic_phy has the ability to adjust PHY Timing settings */ if (driver_data->dynamic_dphy) { - phy_mipi_dphy_get_default_config(clock_in_hz, bpp, dsi->lanes, &cfg); + phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock, + dsi->lanes, &cfg); /* * TODO: @@ -742,15 +741,15 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi) * for these registers, this should be updated. */ - lpx = PS_TO_CYCLE(cfg.lpx, clock_in_hz); - hs_exit = PS_TO_CYCLE(cfg.hs_exit, clock_in_hz); - clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, clock_in_hz); - clk_zero = PS_TO_CYCLE(cfg.clk_zero, clock_in_hz); - clk_post = PS_TO_CYCLE(cfg.clk_post, clock_in_hz); - clk_trail = PS_TO_CYCLE(cfg.clk_trail, clock_in_hz); - hs_prepare = PS_TO_CYCLE(cfg.hs_prepare, clock_in_hz); - hs_zero = PS_TO_CYCLE(cfg.hs_zero, clock_in_hz); - hs_trail = PS_TO_CYCLE(cfg.hs_trail, clock_in_hz); + lpx = PS_TO_CYCLE(cfg.lpx, byte_clock); + hs_exit = PS_TO_CYCLE(cfg.hs_exit, byte_clock); + clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, byte_clock); + clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock); + clk_post = PS_TO_CYCLE(cfg.clk_post, byte_clock); + clk_trail = PS_TO_CYCLE(cfg.clk_trail, byte_clock); + hs_prepare = PS_TO_CYCLE(cfg.hs_prepare, byte_clock); + hs_zero = PS_TO_CYCLE(cfg.hs_zero, byte_clock); + hs_trail = PS_TO_CYCLE(cfg.hs_trail, byte_clock); } /* B D-PHY: D-PHY Master & Slave Analog Block control */ -- 2.40.0