linux-kernel - Re: [RFC PATCH v2] riscv: Add Zawrs support for spinlocks

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Message-ID: <2679603.mvXUDI8C0e@diego>
Date:   Mon, 15 May 2023 00:29:30 +0200
From:   Heiko Stübner <heiko@...ech.de>
To:     'Christoph Muellner' <christoph.muellner@...ll.eu>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Philipp Tomsich <philipp.tomsich@...ll.eu>,
        Aaron Durbin <adurbin@...osinc.com>,
        Randy Dunlap <rdunlap@...radead.org>,
        Atish Patra <atishp@...shpatra.org>
Cc:     David Laight <David.Laight@...lab.com>
Subject: Re: [RFC PATCH v2] riscv: Add Zawrs support for spinlocks

Hi David,

Am Freitag, 24. Juni 2022, 10:52:40 CEST schrieb David Laight:
> From: Christoph Muellner
> > Sent: 23 June 2022 16:30
> > 
> > From: Christoph Müllner <christoph.muellner@...ll.eu>
> > 
> > The current RISC-V code uses the generic ticket lock implementation,
> > that calls the macros smp_cond_load_relaxed() and smp_cond_load_acquire().
> > Currently, RISC-V uses the generic implementation of these macros.
> > This patch introduces a RISC-V specific implementation, of these
> > macros, that peels off the first loop iteration and modifies the waiting
> > loop such, that it is possible to use the WRS.STO instruction of the Zawrs
> > ISA extension to stall the CPU.
> > 
> > The resulting implementation of smp_cond_load_*() will only work for
> > 32-bit or 64-bit types for RV64 and 32-bit types for RV32.
> > This is caused by the restrictions of the LR instruction (RISC-V only
> > has LR.W and LR.D). Compiler assertions guard this new restriction.
> > 
> > This patch uses the existing RISC-V ISA extension framework
> > to detect the presents of Zawrs at run-time.
> > If available a NOP instruction will be replaced by WRS.NTO or WRS.STO.
> > 
> > The whole mechanism is gated by Kconfig setting, which defaults to Y.
> > 
> > The Zawrs specification can be found here:
> > https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
> > 
> > Note, that the Zawrs extension is not frozen or ratified yet.
> > Therefore this patch is an RFC and not intended to get merged.
> > 
> > Changes since v1:
> > * Adding "depends on !XIP_KERNEL" to RISCV_ISA_ZAWRS
> > * Fixing type checking code in __smp_load_reserved*
> > * Adjustments according to the specification change
> > 
> > Signed-off-by: Christoph Müllner <christoph.muellner@...ll.eu>

I'm only addressing the point here were I don't agree with you :-)
Everything else will be in the next version.

[...]

> > +
> > +#define ___smp_load_reservedN(pfx, ptr)					\
> > +({									\
> > +	typeof(*ptr) ___p1;						\
> > +	__asm__ __volatile__ ("lr." pfx "	%[p], %[c]\n"		\
> > +			      : [p]"=&r" (___p1), [c]"+A"(*ptr));	\
> > +	___p1;								\
> > +})
> 
> Isn't that missing the memory reference?
> It either needs a extra memory parameter for 'ptr' or
> a full/partial memory clobber.

Shouldn't the "+A" for *ptr should take care of that?

>From the gcc docs [0]:
	‘+’  Means that this operand is both read and written by the instruction.


Heiko

[0] https://gcc.gnu.org/onlinedocs/gcc/Modifiers.html#index-_002b-in-constraint