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Message-ID: <00e8d677-052c-68a1-3ba6-71aa2315feca@starfivetech.com>
Date: Mon, 15 May 2023 15:35:36 +0800
From: Walker Chen <walker.chen@...rfivetech.com>
To: Xingyu Wu <xingyu.wu@...rfivetech.com>,
<linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
Rob Herring <robh+dt@...nel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
Emil Renner Berthing <kernel@...il.dk>,
Conor Dooley <conor@...nel.org>
CC: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v1 2/2] riscv: dts: starfive: jh7110: Add watchdog node
On 2023/5/9 23:17, Xingyu Wu wrote:
> Add the watchdog node for the Starfive JH7110 SoC.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@...rfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 4c5fdb905da8..47c163ec0bf1 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -469,6 +469,16 @@ sysgpio: pinctrl@...40000 {
> #gpio-cells = <2>;
> };
>
> + watchdog@...70000 {
> + compatible = "starfive,jh7110-wdt";
> + reg = <0x0 0x13070000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
> + <&syscrg JH7110_SYSCLK_WDT_CORE>;
> + clock-names = "apb", "core";
> + resets = <&syscrg JH7110_SYSRST_WDT_APB>,
> + <&syscrg JH7110_SYSRST_WDT_CORE>;
> + };
> +
> aoncrg: clock-controller@...00000 {
> compatible = "starfive,jh7110-aoncrg";
> reg = <0x0 0x17000000 0x0 0x10000>;
Reviewed-by: Walker Chen <walker.chen@...rfivetech.com>
Thanks!
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