lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20230515125458.GT68926@ediswmail.ad.cirrus.com>
Date:   Mon, 15 May 2023 12:54:58 +0000
From:   Charles Keepax <ckeepax@...nsource.cirrus.com>
To:     "Goud, Srinivas" <srinivas.goud@....com>
CC:     "broonie@...nel.org" <broonie@...nel.org>,
        "linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "patches@...nsource.cirrus.com" <patches@...nsource.cirrus.com>
Subject: Re: [PATCH 1/2] spi: spi-cadence: Avoid read of RX FIFO before its
 ready

On Mon, May 15, 2023 at 12:04:38PM +0000, Goud, Srinivas wrote:
> >-----Original Message-----
> >From: Charles Keepax <ckeepax@...nsource.cirrus.com>
> >Sent: Tuesday, May 9, 2023 10:12 PM
> >To: broonie@...nel.org
> >Cc: Goud, Srinivas <srinivas.goud@....com>; linux-spi@...r.kernel.org;
> >linux-kernel@...r.kernel.org; patches@...nsource.cirrus.com
> >Subject: [PATCH 1/2] spi: spi-cadence: Avoid read of RX FIFO before its ready
> >-		while (trans_cnt) {
> >-			cdns_spi_read_rx_fifo(xspi, 1);
> >-
> >-			if (xspi->tx_bytes) {
> >-				if (xspi->txbuf)
> >-					cdns_spi_write(xspi, CDNS_SPI_TXD,
> >-						       *xspi->txbuf++);
> >-				else
> >-					cdns_spi_write(xspi, CDNS_SPI_TXD,
> >0);
> >-				xspi->tx_bytes--;
> >-			}
> >-			trans_cnt--;
> >-		}
> >-		if (!xspi->tx_bytes) {
> >-			/* Fixed delay due to controller limitation with
> >-			 * RX_NEMPTY incorrect status
> >-			 * Xilinx AR:65885 contains more details
> >-			 */
> >-			udelay(10);
> >-			cdns_spi_read_rx_fifo(xspi, xspi->rx_bytes);
> >+		cdns_spi_read_rx_fifo(xspi, trans_cnt);
> Cadence SPI configured in Slave mode,  when threshold is half of FIFO depth cdns_spi_read_rx_fifo() function continuously in read mode, 
> due to this we see incorrect data received on the Master side as Slave is failed to update the TX FIFO on time.

Apologies I am having a little trouble following this are you
saying this part of the patch cases issues for you running in
slave mode?

Thanks,
Charles

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ