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Message-Id: <20230515-topic-rb2-bits-v1-2-a52d154a639d@linaro.org>
Date: Mon, 15 May 2023 15:04:13 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Bhupesh Sharma <bhupesh.sharma@...aro.org>
Cc: Marijn Suijten <marijn.suijten@...ainline.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Konrad Dybcio <konrad.dybcio@...aro.org>
Subject: [PATCH 2/5] arm64: dts: qcom: qrb4210-rb2: Enable display out
The RB2 has a HDMI output via an LT9611UXC bridge. Set it up.
Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
---
arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 88 +++++++++++++++++++++++++++++++-
1 file changed, 87 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts
index 80c6b59c8ff6..9b539720f05d 100644
--- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts
+++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts
@@ -19,6 +19,17 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 {
compatible = "regulator-fixed";
regulator-name = "VREG_HDMI_OUT_1P2";
@@ -109,6 +120,68 @@ &eud {
status = "okay";
};
+&gpi_dma0 {
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+ interrupts-extended = <&tlmm 46 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <&vreg_hdmi_out_1p2>;
+ vcc-supply = <<9611_3v3>;
+
+ pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
+ pinctrl-names = "default";
+ #sound-dai-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l18a_1p232>;
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ status = "okay";
+};
+
&qupv3_id_0 {
status = "okay";
};
@@ -312,11 +385,24 @@ &sleep_clk {
};
&tlmm {
- gpio-reserved-ranges = <37 5>, <43 2>, <47 1>,
+ gpio-reserved-ranges = <43 2>, <47 1>,
<49 1>, <52 1>, <54 1>,
<56 3>, <61 2>, <64 1>,
<68 1>, <72 8>, <96 1>;
+ lt9611_rst_pin: lt9611-rst-state {
+ pins = "gpio41";
+ function = "gpio";
+ input-disable;
+ output-high;
+ };
+
+ lt9611_irq_pin: lt9611-irq-state {
+ pins = "gpio46";
+ function = "gpio";
+ bias-disable;
+ };
+
sdc2_card_det_n: sd-card-det-n-state {
pins = "gpio88";
function = "gpio";
--
2.40.1
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