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Message-ID: <CAOMZO5AiWM64tZgArUL89q5spuLD91R-pnURbfqPU9O0w54sQQ@mail.gmail.com>
Date: Tue, 16 May 2023 19:22:41 -0300
From: Fabio Estevam <festevam@...il.com>
To: Alexander Stein <alexander.stein@...tq-group.com>
Cc: Andrzej Hajda <andrzej.hajda@...el.com>,
Daniel Vetter <daniel@...ll.ch>,
David Airlie <airlied@...il.com>,
dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
Neil Armstrong <neil.armstrong@...aro.org>,
Robert Foss <rfoss@...nel.org>, Marek Vasut <marex@...x.de>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Jonas Karlman <jonas@...boo.se>,
Frieder Schrempf <frieder@...s.de>,
Frieder Schrempf <frieder.schrempf@...tron.de>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>, Sam Ravnborg <sam@...nborg.org>
Subject: Re: [PATCH v2 2/2] drm/bridge: ti-sn65dsi83: Fix enable/disable flow
to meet spec
On Thu, May 4, 2023 at 6:12 AM Alexander Stein
<alexander.stein@...tq-group.com> wrote:
>
> Am Mittwoch, 3. Mai 2023, 18:33:07 CEST schrieb Frieder Schrempf:
> > From: Frieder Schrempf <frieder.schrempf@...tron.de>
> >
> > The datasheet describes the following initialization flow including
> > minimum delay times between each step:
> >
> > 1. DSI data lanes need to be in LP-11 and the clock lane in HS mode
> > 2. toggle EN signal
> > 3. initialize registers
> > 4. enable PLL
> > 5. soft reset
> > 6. enable DSI stream
> > 7. check error status register
> >
> > To meet this requirement we need to make sure the host bridge's
> > pre_enable() is called first by using the pre_enable_prev_first
> > flag.
> >
> > Furthermore we need to split enable() into pre_enable() which covers
> > steps 2-5 from above and enable() which covers step 7 and is called
> > after the host bridge's enable().
> >
> > Signed-off-by: Frieder Schrempf <frieder.schrempf@...tron.de>
>
> Tested-by: Alexander Stein <alexander.stein@...tq-group.com> #TQMa8MxML/MBa8Mx
Should this have a Fixes tag so that it could be backported to stable kernels?
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