linux-kernel - Re: [PATCH v3 3/3] ARM: dts: stm32: fix several DT warnings on stm32mp15

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 17 May 2023 17:41:54 +0200
From:   Marek Vasut <marex@...x.de>
To:     Raphael Gallais-Pou <raphael.gallais-pou@...s.st.com>,
        David Airlie <airlied@...il.com>,
        Daniel Vetter <daniel@...ll.ch>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Alexandre Torgue <alexandre.torgue@...s.st.com>,
        Philippe Cornu <philippe.cornu@...s.st.com>,
        Yannick Fertre <yannick.fertre@...s.st.com>
Cc:     dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org,
        linux-stm32@...md-mailman.stormreply.com,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        kernel@...electronics.com
Subject: Re: [PATCH v3 3/3] ARM: dts: stm32: fix several DT warnings on
 stm32mp15

On 5/17/23 16:35, Raphael Gallais-Pou wrote:

Hi,

> diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
> index 0f1110e42c93..a6e2e20f12fa 100644
> --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
> +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
> @@ -457,8 +457,7 @@ &ltdc {
>   	status = "okay";
>   
>   	port {
> -		ltdc_ep0_out: endpoint@0 {
> -			reg = <0>;
> +		ltdc_ep0_out: endpoint {
>   			remote-endpoint = <&sii9022_in>;
>   		};
>   	};

This LTDC port/endpoint stuff always scares me, because I always feel I 
get it wrong.

I believe the LTDC does have one "port" , correct.

But I think (?) that the LTDC has two endpoints, endpoint@0 for DPI 
(parallel output out of the SoC) and endpoint@1 for DSI (internal 
connection into the DSI serializer) ?

Only one of the endpoints can be connected at a time, but there are 
actually two endpoints in the LTDC port {} node, aren't there ?

So the original description should be OK I think , maybe 
#address/#size-cells are missing instead ?