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Message-ID: <20230517032124.rdh7ehnair3wjuvm@synopsys.com>
Date: Wed, 17 May 2023 03:21:24 +0000
From: Thinh Nguyen <Thinh.Nguyen@...opsys.com>
To: Krishna Kurapati PSSNV <quic_kriskura@...cinc.com>
CC: Johan Hovold <johan@...nel.org>,
Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Felipe Balbi <balbi@...nel.org>,
"linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-msm@...r.kernel.org" <linux-arm-msm@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"quic_pkondeti@...cinc.com" <quic_pkondeti@...cinc.com>,
"quic_ppratap@...cinc.com" <quic_ppratap@...cinc.com>,
"quic_wcheng@...cinc.com" <quic_wcheng@...cinc.com>,
"quic_jackp@...cinc.com" <quic_jackp@...cinc.com>,
"quic_harshq@...cinc.com" <quic_harshq@...cinc.com>,
"ahalaney@...hat.com" <ahalaney@...hat.com>
Subject: Re: [PATCH v8 3/9] usb: dwc3: core: Access XHCI address space
temporarily to read port info
On Wed, May 17, 2023, Krishna Kurapati PSSNV wrote:
>
>
> On 5/16/2023 8:32 PM, Krishna Kurapati PSSNV wrote:
> >
> >
> > On 5/16/2023 5:41 PM, Johan Hovold wrote:
> > > On Sun, May 14, 2023 at 11:19:11AM +0530, Krishna Kurapati wrote:
> > > > Currently host-only capable DWC3 controllers support Multiport.
> > > > Temporarily map XHCI address space for host-only controllers and parse
> > > > XHCI Extended Capabilities registers to read number of usb2 ports and
> > > > usb3 ports present on multiport controller. Each USB Port is at least HS
> > > > capable.
> > > >
> > > > The port info for usb2 and usb3 phy are identified as num_usb2_ports
> > > > and num_usb3_ports. The intention is as follows:
> > > >
> > > > Wherever we need to perform phy operations like:
> > > >
> > > > LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
> > > > {
> > > > phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> > > > phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> > > > }
> > > >
> > > > If number of usb2 ports is 3, loop can go from index 0-2 for
> > > > usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
> > > > if the first 2 ports are SS capable or some other ports like (2 and 3)
> > > > are SS capable. So instead, num_usb2_ports is used to loop around all
> > > > phy's (both hs and ss) for performing phy operations. If any
> > > > usb3_generic_phy turns out to be NULL, phy operation just bails out.
> > > >
> > > > num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
> > > > phy's as we need to know how many SS capable ports are there for this.
> > > >
> > > > Signed-off-by: Krishna Kurapati <quic_kriskura@...cinc.com>
> > > > ---
> > > > drivers/usb/dwc3/core.c | 113 ++++++++++++++++++++++++++++++++++++++++
> > > > drivers/usb/dwc3/core.h | 17 +++++-
> > > > 2 files changed, 129 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > index 0beaab932e7d..e983aef1fb93 100644
> > > > --- a/drivers/usb/dwc3/core.c
> > > > +++ b/drivers/usb/dwc3/core.c
> > > > @@ -1767,6 +1767,104 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
> > > > return 0;
> > > > }
> > > > +/**
> > > > + * dwc3_xhci_find_next_ext_cap - Find the offset of the
> > > > extended capabilities
> > > > + * with capability ID id.
> > > > + *
> > > > + * @base: PCI MMIO registers base address.
> > > > + * @start: address at which to start looking, (0 or
> > > > HCC_PARAMS to start at
> > > > + * beginning of list)
> > > > + * @id: Extended capability ID to search for, or 0 for the next
> > > > + * capability
> > > > + *
> > > > + * Returns the offset of the next matching extended capability
> > > > structure.
> > > > + * Some capabilities can occur several times, e.g., the
> > > > XHCI_EXT_CAPS_PROTOCOL,
> > > > + * and this provides a way to find them all.
> > > > + */
> > > > +static int dwc3_xhci_find_next_ext_cap(void __iomem *base, u32
> > > > start, int id)
> > > > +{
> > > > + u32 val;
> > > > + u32 next;
> > > > + u32 offset;
> > > > +
> > > > + offset = start;
> > > > + if (!start || start == XHCI_HCC_PARAMS_OFFSET) {
> > > > + val = readl(base + XHCI_HCC_PARAMS_OFFSET);
> > > > + if (val == ~0)
> > > > + return 0;
> > > > + offset = XHCI_HCC_EXT_CAPS(val) << 2;
> > > > + if (!offset)
> > > > + return 0;
> > > > + }
> > > > + do {
> > > > + val = readl(base + offset);
> > > > + if (val == ~0)
> > > > + return 0;
> > > > + if (offset != start && (id == 0 ||
> > > > XHCI_EXT_CAPS_ID(val) == id))
> > > > + return offset;
> > > > +
> > > > + next = XHCI_EXT_CAPS_NEXT(val);
> > > > + offset += next << 2;
> > > > + } while (next);
> > > > +
> > > > + return 0;
> > > > +}
> > >
> > > You should not make another copy of xhci_find_next_ext_cap(), but rather
> > > use it directly.
> > >
> > > We already have drivers outside of usb/host using this function so it
> > > should be fine to do the same for now:
> > >
> > > #include "../host/xhci-ext-caps.h"
> > >
> > Hi Johan,
> >
> > This was the approach which we followed when we first introduced the
> > patch [1]. But Thinh suggested to duplicate code so that we can avoid
> > any dependency on xhci (which seems to be right). So since its just one
> > function, I duplicated it here.
> >
> Hi Thinh,
>
> Would like to know your opinion here on how to proceed further.
>
> Regards,
> Krishna,
Please keep them separated. The xhci-ext-caps.h is for xhci driver only.
It's not meant to be exposed to other drivers. Same with other *.h files
under drivers/usb/host.
Thanks,
Thinh
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