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Date:   Wed, 17 May 2023 11:14:28 +0530
From:   Manivannan Sadhasivam <mani@...nel.org>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>
Cc:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        "Borislav Petkov (AMD)" <bp@...en8.de>,
        Marijn Suijten <marijn.suijten@...ainline.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Fix SM8550 description

On Wed, May 17, 2023 at 04:18:49AM +0200, Konrad Dybcio wrote:
> SM8550 (LLCCv4.1) has 4 register regions, this was not described
> between its addition and the restructurization that happened in
> the commit referenced in the fixes tag.
> 
> Fix it.
> 
> Fixes: 43aa006e074c ("dt-bindings: arm: msm: Fix register regions used for LLCC banks")

I'm not sure if the Fixes tag should point to the patch adding SM8550 support or
the restructuring patch.

> Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>

But the change LGTM!

Acked-by: Manivannan Sadhasivam <mani@...nel.org>

- Mani

> ---
>  Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> index d8b91944180a..44892aa589fd 100644
> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> @@ -129,6 +129,7 @@ allOf:
>                - qcom,sm8250-llcc
>                - qcom,sm8350-llcc
>                - qcom,sm8450-llcc
> +              - qcom,sm8550-llcc
>      then:
>        properties:
>          reg:
> 
> -- 
> 2.40.1
> 

-- 
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