linux-kernel - Re: [PATCH V6 5/6] drm: bridge: samsung-dsim: Dynamically configure DPHY timing

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Date:   Wed, 17 May 2023 16:57:50 +0530
From:   Jagan Teki <jagan@...rulasolutions.com>
To:     Adam Ford <aford173@...il.com>
Cc:     dri-devel@...ts.freedesktop.org, aford@...conembedded.com,
        Lucas Stach <l.stach@...gutronix.de>,
        Chen-Yu Tsai <wenst@...omium.org>,
        Frieder Schrempf <frieder.schrempf@...tron.de>,
        Michael Walle <michael@...le.cc>,
        Andrzej Hajda <andrzej.hajda@...el.com>,
        Neil Armstrong <neil.armstrong@...aro.org>,
        Robert Foss <rfoss@...nel.org>,
        Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
        Jonas Karlman <jonas@...boo.se>,
        Jernej Skrabec <jernej.skrabec@...il.com>,
        David Airlie <airlied@...il.com>,
        Daniel Vetter <daniel@...ll.ch>,
        Inki Dae <inki.dae@...sung.com>,
        Marek Szyprowski <m.szyprowski@...sung.com>,
        Marek Vasut <marex@...x.de>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH V6 5/6] drm: bridge: samsung-dsim: Dynamically configure
 DPHY timing

On Tue, May 16, 2023 at 5:27 AM Adam Ford <aford173@...il.com> wrote:
>
> The DPHY timings are currently hard coded. Since the input
> clock can be variable, the phy timings need to be variable
> too.  To facilitate this, we need to cache the hs_clock
> based on what is generated from the PLL.
>
> The phy_mipi_dphy_get_default_config_for_hsclk function
> configures the DPHY timings in pico-seconds, and a small macro
> converts those timings into clock cycles based on the hs_clk.
>
> Signed-off-by: Adam Ford <aford173@...il.com>
> Signed-off-by: Lucas Stach <l.stach@...gutronix.de>
> Tested-by: Chen-Yu Tsai <wenst@...omium.org>
> Tested-by: Frieder Schrempf <frieder.schrempf@...tron.de>
> Reviewed-by: Frieder Schrempf <frieder.schrempf@...tron.de>
> Tested-by: Michael Walle <michael@...le.cc>
> ---
>  drivers/gpu/drm/bridge/samsung-dsim.c | 57 +++++++++++++++++++++++----
>  include/drm/bridge/samsung-dsim.h     |  1 +
>  2 files changed, 51 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> index 08266303c261..3944b7cfbbdf 100644
> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> @@ -218,6 +218,8 @@
>
>  #define OLD_SCLK_MIPI_CLK_NAME         "pll_clk"
>
> +#define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000000000ULL)
> +
>  static const char *const clk_names[5] = {
>         "bus_clk",
>         "sclk_mipi",
> @@ -651,6 +653,8 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
>                 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
>         } while ((reg & DSIM_PLL_STABLE) == 0);
>
> +       dsi->hs_clock = fout;
> +
>         return fout;
>  }
>
> @@ -698,13 +702,46 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi)
>         const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
>         const unsigned int *reg_values = driver_data->reg_values;
>         u32 reg;
> +       struct phy_configure_opts_mipi_dphy cfg;
> +       int clk_prepare, lpx, clk_zero, clk_post, clk_trail;
> +       int hs_exit, hs_prepare, hs_zero, hs_trail;
> +       unsigned long long byte_clock = dsi->hs_clock / 8;
>
>         if (driver_data->has_freqband)
>                 return;
>
> +       phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock,
> +                                                  dsi->lanes, &cfg);
> +
> +       /*
> +        * TODO:
> +        * The tech reference manual for i.MX8M Mini/Nano/Plus

Does it mean, Applications Processor Reference Manual? better add it
clear reference.

> +        * doesn't state what the definition of the PHYTIMING
> +        * bits are beyond their address and bit position.
> +        * After reviewing NXP's downstream code, it appears
> +        * that the various PHYTIMING registers take the number
> +        * of cycles and use various dividers on them.  This
> +        * calculation does not result in an exact match to the
> +        * downstream code, but it is very close, and it appears
> +        * to sync at a variety of resolutions. If someone
> +        * can get a more accurate mathematical equation needed
> +        * for these registers, this should be updated.
> +        */
> +
> +       lpx = PS_TO_CYCLE(cfg.lpx, byte_clock);
> +       hs_exit = PS_TO_CYCLE(cfg.hs_exit, byte_clock);
> +       clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, byte_clock);
> +       clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock);
> +       clk_post = PS_TO_CYCLE(cfg.clk_post, byte_clock);
> +       clk_trail = PS_TO_CYCLE(cfg.clk_trail, byte_clock);
> +       hs_prepare = PS_TO_CYCLE(cfg.hs_prepare, byte_clock);
> +       hs_zero = PS_TO_CYCLE(cfg.hs_zero, byte_clock);
> +       hs_trail = PS_TO_CYCLE(cfg.hs_trail, byte_clock);

I think we can do some kind of negotiation has done similar in bsp by
taking inputs from bit_clk  and PLL_1432X table. Did you try this? we
thought this approach while writing dsim to support dynamic dphy.

Thanks,
Jagan.