linux-kernel - Re: [PATCH] arm64: dts: microchip: add missing cache properties

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Date:   Wed, 17 May 2023 13:38:39 +0200
From:   Steen Hegelund <steen.hegelund@...rochip.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
CC:     Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Lars Povlsen <lars.povlsen@...rochip.com>,
        Daniel Machon <daniel.machon@...rochip.com>,
        <UNGLinuxDriver@...rochip.com>, <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] arm64: dts: microchip: add missing cache properties

Hi Krzysztof,

I would love to do that, but I am not familiar with the procedure, so maybe you
could help me out?

This is my understanding of what I need to do:

Clone the upstream repo listed in MAINTAINERS:

git clone git@...hub.com:microchip-ung/linux-upstream.git
cd linux-upstream
git checkout sparx5-next

Fetch the latest mainline tag from upstream:

git fetch git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git tag\
 v6.4-rc2 --no-tags

Rebase the current branch on top of that tag:

git rebase v6.4-rc2

Use b4 to fetch and apply the mail thread patch series:

b4 shazam -tsl 20230421223155.115339-1-krzysztof.kozlowski@...aro.org

Tag the current work for inclusion in the next kernel version with a decription:

git tag -s sparx5-dt-6.5

Push work that to the public repo:

git push origin sparx5-dt-6.5

Create a pull request (to stdout) to be included in an email to the maintainers:

git request-pull v6.4-rc2 origin sparx5-dt-6.5

Send this PR to the maintainers and CC co-maintainers.

Is this the correct procedure?
Who should I send the PR email to (is there a list somewhere)?
 
BR
Steen

On Tue, 2023-05-16 at 18:30 +0200, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
> 
> On 22/04/2023 00:31, Krzysztof Kozlowski wrote:
> > As all level 2 and level 3 caches are unified, add required
> > cache-unified and cache-level properties to fix warnings like:
> > 
> >   sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property
> > 
> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> > 
> > ---
> 
> Anyone from Microchip picking this up?
> 
> Best regards,
> Krzysztof
>