linux-kernel - Re: [PATCH v2 3/3] arm64: dts: microchip: sparx5: add missing L1/L2 cache information

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Date:   Wed, 17 May 2023 14:26:38 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Robert Marko <robert.marko@...tura.hr>, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, lars.povlsen@...rochip.com,
        Steen.Hegelund@...rochip.com, daniel.machon@...rochip.com,
        UNGLinuxDriver@...rochip.com, arnd@...db.de,
        alexandre.belloni@...tlin.com, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Conor Dooley <conor@...nel.org>
Cc:     luka.perkov@...tura.hr
Subject: Re: [PATCH v2 3/3] arm64: dts: microchip: sparx5: add missing L1/L2
 cache information

On 21/02/2023 11:50, Robert Marko wrote:
> Currently, when booting on SparX-5 you will get the following error:
> [    0.050132] Early cacheinfo failed, ret = -22
> 
> This is due to L2 cache node missing cache-level property to indicate its
> level, so populate it to let the kernel know its L2 cache.
> 
> However, that alone is enough to get rid of the error, but then the
> following warnings appear:
> [    0.050162] cacheinfo: Unable to detect cache hierarchy for CPU 0
> [    0.093256] cacheinfo: Unable to detect cache hierarchy for CPU 1
> 

This did not apply, skipped.

Best regards,
Krzysztof