linux-kernel - Re: [PATCH] irqchip/gic-v3: workaround for ASR8601 when reading mpidr

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Message-ID: <86mt22ksqc.wl-maz@kernel.org>
Date:   Thu, 18 May 2023 08:23:55 +0100
From:   Marc Zyngier <maz@...nel.org>
To:     Yan Zheng（严政） <zhengyan@...micro.com>
Cc:     "tglx@...utronix.de" <tglx@...utronix.de>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Gao Meitao（高玫涛） 
        <meitaogao@...micro.com>,
        "Zhou Qiao(周侨)" <qiaozhou@...micro.com>,
        "Zhang Zhizhou(张治洲)" 
        <zhizhouzhang@...micro.com>
Subject: Re: [PATCH] irqchip/gic-v3: workaround for ASR8601 when reading mpidr

On Thu, 18 May 2023 04:15:54 +0100,
Yan Zheng（严政） <zhengyan@...micro.com> wrote:
> 
> 
> 
> > -----Original Message-----
> > From: Marc Zyngier [mailto:maz@...nel.org]
> > Sent: Wednesday, May 17, 2023 8:59 PM
> > To: Yan Zheng（严政） <zhengyan@...micro.com>
> > Cc: tglx@...utronix.de; linux-kernel@...r.kernel.org; Gao Meitao（高玫涛）
> > <meitaogao@...micro.com>; Zhou Qiao(周侨) <qiaozhou@...micro.com>;
> > Zhang Zhizhou(张治洲) <zhizhouzhang@...micro.com>
> > Subject: Re: [PATCH] irqchip/gic-v3: workaround for ASR8601 when reading
> > mpidr
> > 
> > On Wed, 17 May 2023 11:45:22 +0100,
> > Yan Zheng（严政） <zhengyan@...micro.com> wrote:
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: Marc Zyngier [mailto:maz@...nel.org]
> > > > Sent: Wednesday, May 17, 2023 4:32 PM
> > > > To: Yan Zheng（严政） <zhengyan@...micro.com>
> > > > Cc: tglx@...utronix.de; linux-kernel@...r.kernel.org; Gao
> > > > Meitao（高玫涛）
> > > > <meitaogao@...micro.com>; Zhou Qiao(周侨) <qiaozhou@...micro.com>;
> > > > Zhang Zhizhou(张治洲) <zhizhouzhang@...micro.com>
> > > > Subject: Re: [PATCH] irqchip/gic-v3: workaround for ASR8601 when
> > > > reading mpidr
> > > >
> > > > On Wed, 17 May 2023 08:55:00 +0100,
> > > > zhengyan <zhengyan@...micro.com> wrote:
> > > > >
> > > > > This patch add workaround for ASR8601, which uses an armv8.2
> > > > > processor with a gic-500. ARMv8.2 uses Multiprocessor Affinity
> > > > > Register to identify the logical address of the core by
> > > > > | cluster | core | thread |.
> > > >
> > > > Not quite. The ARMv8.2 architecture doesn't say *any* of that. It is
> > > > ARM's
> > > > *implementations* that follow this scheme.
> > > >
> > >
> > > Really thank you for rapid response,
> > > Yes, as arm documents
> > > https://developer.arm.com/docuentation/ka002107/latest said
> > 
> > This page doesn't exist.
> > 
> 
> Sorry for my mistake,
> https://developer.arm.com/documentation/ka002107/latest
> extract from the docs:
> The Arm-v8.0 CPUs use affinity 0 for a CPU and affinity 1 for a cluster. 
> All Arm-v8.2 CPUs use affinity 2 for a cluster, 1 for a CPU, and 0 for a thread.
> The GIC-500 does not support affinity 2. Therefore, the GIC-500 cannot route 
> Shared Peripheral Interrupts (SPIs) or Software Generated Interrupts (SGIs) 
> correctly for Arm-v8.2 CPUs. 
> The GIC-500 does not have correct buses to connect the system together.

All these are implementations. Nothing to do with the architecture
(which only mentions the notion of 'cluster' when talking about
caches).

Anyway, let's move on.

>
> > > It comes from armv8.2 get 3 types for affinity (arm v8.0 cpus only get
> > > 2 types) And it's an implementations issue.
> > 
> > Again, this has nothing to do with the ARMv8.2 architecture. Nor the
> > ARMv8.0 architecture. Please read the ARM ARM, which says absolutely
> > *nothing* of what the various affinity levels are for.
> > 
> 
> As the extract from pervious part mentioned,
> It seems like this issue related to that? I just want to mention that
> this issue is cause by HW choice in the commit message.

You can say that GIC500 is incompatible with ARMv8.2 implementations
from ARM, and that a workaround is needed for that.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.