| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Thu, 18 May 2023 11:55:09 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Bjorn Andersson <quic_bjorande@...cinc.com>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>
Cc: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] arm64: dts: qcom: sc8280xp: Add SDC2 and enable on CRD
On 18.05.2023 01:52, Bjorn Andersson wrote:
> The CRD has Micro SD slot, introduce the necessary DeviceTree nodes for
> enabling this.
>
> Signed-off-by: Bjorn Andersson <quic_bjorande@...cinc.com>
> ---
>
> Changes since v1:
> - Order of pinctr-N and pinctrl-names
> - Reset GCC_SDCC2_BCR and not sdc4
b4 diff 20230517235217.1728548-1-quic_bjorande@...cinc.com also reveals:
- move cd-gpios
- add interconnect OPP properties
nevertheless:
Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
Konrad
>
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 81 +++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 43 ++++++++++++
> 2 files changed, 124 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> index 5b25d54b9591..ff9cebbccfcb 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> @@ -308,6 +308,13 @@ vreg_l1c: ldo1 {
> regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> };
>
> + vreg_l6c: ldo6 {
> + regulator-name = "vreg_l6c";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> vreg_l7c: ldo7 {
> regulator-name = "vreg_l7c";
> regulator-min-microvolt = <2504000>;
> @@ -318,6 +325,13 @@ vreg_l7c: ldo7 {
> RPMH_REGULATOR_MODE_HPM>;
> };
>
> + vreg_l9c: ldo9 {
> + regulator-name = "vreg_l9c";
> + regulator-min-microvolt = <2960000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> vreg_l13c: ldo13 {
> regulator-name = "vreg_l13c";
> regulator-min-microvolt = <3072000>;
> @@ -600,6 +614,19 @@ &remoteproc_nsp0 {
> status = "okay";
> };
>
> +&sdc2 {
> + pinctrl-0 = <&sdc2_default_state>;
> + pinctrl-1 = <&sdc2_sleep_state>;
> + pinctrl-names = "default", "sleep";
> +
> + vmmc-supply = <&vreg_l9c>;
> + vqmmc-supply = <&vreg_l6c>;
> +
> + cd-gpios = <&tlmm 131 GPIO_ACTIVE_LOW>;
> +
> + status = "okay";
> +};
> +
> &uart17 {
> compatible = "qcom,geni-debug-uart";
>
> @@ -842,6 +869,60 @@ wake-n-pins {
> };
> };
>
> + sdc2_default_state: sdc2-default-state {
> + clk-pins {
> + pins = "sdc2_clk";
> + drive-strength = <16>;
> + bias-disable;
> + };
> +
> + cmd-pins {
> + pins = "sdc2_cmd";
> + drive-strength = <16>;
> + bias-pull-up;
> + };
> +
> + data-pins {
> + pins = "sdc2_data";
> + drive-strength = <16>;
> + bias-pull-up;
> + };
> +
> + card-detect-pins {
> + pins = "gpio131";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> + };
> +
> + sdc2_sleep_state: sdc2-sleep-state {
> + clk-pins {
> + pins = "sdc2_clk";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cmd-pins {
> + pins = "sdc2_cmd";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + data-pins {
> + pins = "sdc2_data";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + card-detect-pins {
> + pins = "gpio131";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> + };
> +
> tpad_default: tpad-default-state {
> int-n-pins {
> pins = "gpio182";
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 8fa9fbfe5d00..3711f109aeaf 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -2815,6 +2815,49 @@ data-pins {
> };
> };
>
> + sdc2: mmc@...4000 {
> + compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0 0x08804000 0 0x1000>;
> +
> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> + <&gcc GCC_SDCC2_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "core", "xo";
> + resets = <&gcc GCC_SDCC2_BCR>;
> + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
> + interconnect-names = "sdhc-ddr","cpu-sdhc";
> + iommus = <&apps_smmu 0x4e0 0x0>;
> + power-domains = <&rpmhpd SC8280XP_CX>;
> + operating-points-v2 = <&sdc2_opp_table>;
> + bus-width = <4>;
> + dma-coherent;
> +
> + status = "disabled";
> +
> + sdc2_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <1800000 400000>;
> + opp-avg-kBps = <100000 0>;
> + };
> +
> + opp-202000000 {
> + opp-hz = /bits/ 64 <202000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + opp-peak-kBps = <5400000 1600000>;
> + opp-avg-kBps = <200000 0>;
> + };
> + };
> + };
> +
> usb_0_qmpphy: phy@...b000 {
> compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
> reg = <0 0x088eb000 0 0x4000>;
Powered by blists - more mailing lists