lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Fri, 19 May 2023 23:09:29 +0200
From:   Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To:     Dmitry Rokosov <ddrokosov@...rdevices.ru>,
        krzysztof.kozlowski+dt@...aro.org
Cc:     neil.armstrong@...aro.org, jbrunet@...libre.com,
        mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
        khilman@...libre.com, jian.hu@...ogic.com, kernel@...rdevices.ru,
        rockosov@...il.com, linux-amlogic@...ts.infradead.org,
        linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v15 5/6] dt-bindings: clock: meson: add A1 Peripherals
 clock controller bindings

Hi Krzysztof and Dmitry,

On Wed, May 17, 2023 at 3:33 PM Dmitry Rokosov <ddrokosov@...rdevices.ru> wrote:
[...]
> +  clocks:
> +    items:
> +      - description: input fixed pll div2
> +      - description: input fixed pll div3
> +      - description: input fixed pll div5
> +      - description: input fixed pll div7
> +      - description: input hifi pll
> +      - description: input oscillator (usually at 24MHz)
> +
> +  clock-names:
> +    items:
> +      - const: fclk_div2
> +      - const: fclk_div3
> +      - const: fclk_div5
> +      - const: fclk_div7
> +      - const: hifi_pll
> +      - const: xtal
This IP block has at least one additional input called "sys_pll_div16".
My understanding is that the "sys_pll_div16" clock is generated by the
CPU clock controller. Support for the CPU clock controller
(dt-bindings and a driver) will be added at a later time by Dmitry.
How can we manage incrementally implementing the clock controllers?
>From a hardware perspective the "sys_pll_div16" input is mandatory.
How to manage this in the .dts patches then (for example: does this
mean that Dmitry can only add the clock controller to the .dts when
all clock controller bindings have been implemented - or is there
another way)?


Best regards,
Martin

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ