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Message-ID: <20230519-smokeless-guileless-2a71cae06509@wendy>
Date: Fri, 19 May 2023 15:16:49 +0100
From: Conor Dooley <conor.dooley@...rochip.com>
To: Torsten Duwe <duwe@....de>
CC: Xingyu Wu <xingyu.wu@...rfivetech.com>,
<linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<yanhong.wang@...rfivetech.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Conor Dooley <conor@...nel.org>,
Emil Renner Berthing <kernel@...il.dk>,
Rob Herring <robh+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Hal Feng <hal.feng@...rfivetech.com>,
William Qiu <william.qiu@...rfivetech.com>,
<linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>
Subject: Re: [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock
generator
On Fri, May 19, 2023 at 03:57:33PM +0200, Torsten Duwe wrote:
> On Fri, May 12, 2023 at 10:20:30AM +0800, Xingyu Wu wrote:
> [...]
> > #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
> > #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
> >
> > +/* PLL clocks */
> > +#define JH7110_CLK_PLL0_OUT 0
> > +#define JH7110_CLK_PLL1_OUT 1
> > +#define JH7110_CLK_PLL2_OUT 2
>
> In U-Boot commit 58c9c60b Yanhong Wang added:
>
> +
> +#define JH7110_SYSCLK_PLL0_OUT 190
> +#define JH7110_SYSCLK_PLL1_OUT 191
> +#define JH7110_SYSCLK_PLL2_OUT 192
> +
> +#define JH7110_SYSCLK_END 193
>
> in that respective file.
>
> > +#define JH7110_PLLCLK_END 3
> > +
> > /* SYSCRG clocks */
> > #define JH7110_SYSCLK_CPU_ROOT 0
>
> If the symbolic names referred to the same items, would it be possible
> to keep the two files in sync somehow?
Ohh, that's not good.. If you pass the U-Boot dtb to Linux it won't
understand the numbering. The headers are part of the dt-binding :/
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